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authorSteve Reinhardt <steve.reinhardt@amd.com>2010-09-09 14:40:18 -0400
committerSteve Reinhardt <steve.reinhardt@amd.com>2010-09-09 14:40:18 -0400
commit71aca6d29e686ecdec2828c8be1989f74d9b28d3 (patch)
tree1ff5b36c08f5e1c3853208674608d141e2924c57 /src/mem/cache/mshr_queue.hh
parent7c4dc4491a6367888154129d2799b5f564ecb0d9 (diff)
downloadgem5-71aca6d29e686ecdec2828c8be1989f74d9b28d3.tar.xz
cache: coherence protocol enhancements & bug fixes
Allow lower-level caches (e.g., L2 or L3) to pass exclusive copies to higher levels (e.g., L1). This eliminates a lot of unnecessary upgrade transactions on read-write sequences to non-shared data. Also some cleanup of MSHR coherence handling and multiple bug fixes.
Diffstat (limited to 'src/mem/cache/mshr_queue.hh')
-rw-r--r--src/mem/cache/mshr_queue.hh2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/cache/mshr_queue.hh b/src/mem/cache/mshr_queue.hh
index f481ca471..d8c495679 100644
--- a/src/mem/cache/mshr_queue.hh
+++ b/src/mem/cache/mshr_queue.hh
@@ -160,7 +160,7 @@ class MSHRQueue
* readyList. Deallocates the MSHR if it does not expect a response.
* @param mshr The MSHR to mark in service.
*/
- void markInService(MSHR *mshr);
+ void markInService(MSHR *mshr, PacketPtr pkt);
/**
* Mark an in service entry as pending, used to resend a request.