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author | Ron Dreslinski <rdreslin@umich.edu> | 2006-11-22 20:20:38 -0500 |
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committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-11-22 20:20:38 -0500 |
commit | 28fd4ab39fe7991d335e8496ed2b3434db61140d (patch) | |
tree | fcd7b6b5e1602edefe75b4b7d3a447598c65ecea /src/mem/cache/prefetch | |
parent | 719416b60ff2ab60403d22b6c7f75139b9535d8c (diff) | |
download | gem5-28fd4ab39fe7991d335e8496ed2b3434db61140d.tar.xz |
Do a functional access to levels above on a read as a temporary solution for L2's in FS
Fix a small writeback bug when missing in the L2 in atomic mode
src/mem/bus.cc:
Fix a comment to make sense
src/mem/cache/cache_impl.hh:
Do a functional access to levels above on a read as a temporary solution for L2's in FS
Also fix a small writeback miss in L2 issue
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
Do a functional access to levels above on a read as a temporary solution for L2's in FS
tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt:
tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt:
Update ref's for writeback changes
--HG--
extra : convert_revision : 937febd577b16b7fd97a5a68acaf53541828a251
Diffstat (limited to 'src/mem/cache/prefetch')
0 files changed, 0 insertions, 0 deletions