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| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-09 14:40:19 -0400 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-09 14:40:19 -0400 |
| commit | 12497284949cb5418e6bc403723c034aee655666 (patch) | |
| tree | 425830586f5c32fe2674a3eb998678ef633d2d6e /src/mem/packet.cc | |
| parent | 6dc599ea9bae9cb56ca81094b37009f5a14ebdff (diff) | |
| download | gem5-12497284949cb5418e6bc403723c034aee655666.tar.xz | |
cache: fail SC when invalidated while waiting for bus
Corrects an oversight in cset f97b62be544f. The fix there only
failed queued SCUpgradeReq packets that encountered an
invalidation, which meant that the upgrade had to reach the L2
cache. To handle pending requests in the L1 we must similarly
fail StoreCondReq packets too.
Diffstat (limited to 'src/mem/packet.cc')
| -rw-r--r-- | src/mem/packet.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mem/packet.cc b/src/mem/packet.cc index 5eb2ecc4b..d0b1fed83 100644 --- a/src/mem/packet.cc +++ b/src/mem/packet.cc @@ -123,6 +123,10 @@ MemCmd::commandInfo[] = { SET6(IsWrite, NeedsExclusive, IsLlsc, IsRequest, NeedsResponse, HasData), StoreCondResp, "StoreCondReq" }, + /* StoreCondFailReq: generates failing StoreCondResp ASAP */ + { SET6(IsWrite, NeedsExclusive, IsLlsc, + IsRequest, NeedsResponse, HasData), + StoreCondResp, "StoreCondFailReq" }, /* StoreCondResp */ { SET4(IsWrite, NeedsExclusive, IsLlsc, IsResponse), InvalidCmd, "StoreCondResp" }, |