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authorNilay Vaish <nilay@cs.wisc.edu>2014-09-01 16:55:45 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2014-09-01 16:55:45 -0500
commitcee8faaad066cda6710904b5190e7287ff9356af (patch)
tree26e2e80ef32a9d82cd6f740d39d15aa229620e5a /src/mem/protocol/MESI_Two_Level-L1cache.sm
parentb1d3873ec52692b0442666718da4175379697bb2 (diff)
downloadgem5-cee8faaad066cda6710904b5190e7287ff9356af.tar.xz
ruby: slicc: change the way configurable members are specified
There are two changes this patch makes to the way configurable members of a state machine are specified in SLICC. The first change is that the data member declarations will need to be separated by a semi-colon instead of a comma. Secondly, the default value to be assigned would now use SLICC's assignment operator i.e. ':='.
Diffstat (limited to 'src/mem/protocol/MESI_Two_Level-L1cache.sm')
-rw-r--r--src/mem/protocol/MESI_Two_Level-L1cache.sm20
1 files changed, 10 insertions, 10 deletions
diff --git a/src/mem/protocol/MESI_Two_Level-L1cache.sm b/src/mem/protocol/MESI_Two_Level-L1cache.sm
index a202a8deb..96c1699b7 100644
--- a/src/mem/protocol/MESI_Two_Level-L1cache.sm
+++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm
@@ -27,16 +27,16 @@
*/
machine(L1Cache, "MESI Directory L1 Cache CMP")
- : Sequencer * sequencer,
- CacheMemory * L1Icache,
- CacheMemory * L1Dcache,
- Prefetcher * prefetcher = 'NULL',
- int l2_select_num_bits,
- Cycles l1_request_latency = 2,
- Cycles l1_response_latency = 2,
- Cycles to_l2_latency = 1,
- bool send_evictions,
- bool enable_prefetch = "False"
+ : Sequencer * sequencer;
+ CacheMemory * L1Icache;
+ CacheMemory * L1Dcache;
+ Prefetcher * prefetcher;
+ int l2_select_num_bits;
+ Cycles l1_request_latency := 2;
+ Cycles l1_response_latency := 2;
+ Cycles to_l2_latency := 1;
+ bool send_evictions;
+ bool enable_prefetch := "False";
{
// NODE L1 CACHE
// From this node's L1 cache TO the network