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| author | Michael LeBeane <michael.lebeane@amd.com> | 2016-10-26 22:48:37 -0400 |
|---|---|---|
| committer | Michael LeBeane <michael.lebeane@amd.com> | 2016-10-26 22:48:37 -0400 |
| commit | 48e43c9ad1cd292b494f3d05f9d13845dd1a6d1e (patch) | |
| tree | db08e7d64d0431fe887c490a0b79f8b524131f15 /src/mem/protocol/RubySlicc_Types.sm | |
| parent | 96905971f26e5218baebf8f953f05a9b341f9cc6 (diff) | |
| download | gem5-48e43c9ad1cd292b494f3d05f9d13845dd1a6d1e.tar.xz | |
ruby: Allow multiple outstanding DMA requests
DMA sequencers and protocols can currently only issue one DMA access at
a time. This patch implements the necessary functionality to support
multiple outstanding DMA requests in Ruby.
Diffstat (limited to 'src/mem/protocol/RubySlicc_Types.sm')
| -rw-r--r-- | src/mem/protocol/RubySlicc_Types.sm | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm index e8a739eb4..27a045d29 100644 --- a/src/mem/protocol/RubySlicc_Types.sm +++ b/src/mem/protocol/RubySlicc_Types.sm @@ -220,8 +220,8 @@ structure (WireBuffer, inport="yes", outport="yes", external = "yes") { } structure (DMASequencer, external = "yes") { - void ackCallback(); - void dataCallback(DataBlock); + void ackCallback(Addr); + void dataCallback(DataBlock,Addr); void recordRequestType(CacheRequestType); } |