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| author | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-08-20 11:46:12 -0700 |
|---|---|---|
| committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-08-20 11:46:12 -0700 |
| commit | 54d76f0ce5d721ad3b4de168db98054844e634cc (patch) | |
| tree | 19b74bf031e5aa9ecae18b7a1a0d36b5e0fc466c /src/mem/protocol/RubySlicc_Types.sm | |
| parent | a3b4b9b3e3f8a1462b34d758199312d33af4b0c7 (diff) | |
| download | gem5-54d76f0ce5d721ad3b4de168db98054844e634cc.tar.xz | |
ruby: Fixed L2 cache miss profiling
Fixed L2 cache miss profiling for the MOESI_CMP_token protocol
Diffstat (limited to 'src/mem/protocol/RubySlicc_Types.sm')
| -rw-r--r-- | src/mem/protocol/RubySlicc_Types.sm | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm index 7fc817600..8dcdabeb8 100644 --- a/src/mem/protocol/RubySlicc_Types.sm +++ b/src/mem/protocol/RubySlicc_Types.sm @@ -126,6 +126,11 @@ external_type(CacheMemory) { void changePermission(Address, AccessPermission); bool isTagPresent(Address); void profileMiss(CacheMsg); + + void profileGenericRequest(GenericRequestType, + AccessModeType, + PrefetchBit); + void setMRU(Address); } |