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| author | Tiago Muck <tiago.muck@arm.com> | 2019-02-19 15:58:33 -0600 |
|---|---|---|
| committer | Tiago Mück <tiago.muck@arm.com> | 2019-05-14 22:01:12 +0000 |
| commit | 496d5ed3e1f7dad42b0c2ebe0050d84621be8f99 (patch) | |
| tree | 0ec4954d60e37d1bfe595aa6b1c7a6913a27f005 /src/mem/ruby/slicc_interface/AbstractController.cc | |
| parent | 42e55cdafdac41830839ac2584d99a8dd5e3d95e (diff) | |
| download | gem5-496d5ed3e1f7dad42b0c2ebe0050d84621be8f99.tar.xz | |
mem-ruby: Hit latencies defined by the controllers
Removed the icache/dcache hit latency parameters from the Sequencer.
They were replaced by the mandatory queue enqueue latency that is now
defined by the top-level cache controller. By default, the latency is
defined by the mandatory_queue_latency parameter. When the latency
depends on specific protocol states or on the request type, the protocol
may override the mandatoryQueueLatency function.
Change-Id: I72e57a7ea49501ef81dc7f591bef14134274647c
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18413
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/mem/ruby/slicc_interface/AbstractController.cc')
| -rw-r--r-- | src/mem/ruby/slicc_interface/AbstractController.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc index 68edcba59..c953e8257 100644 --- a/src/mem/ruby/slicc_interface/AbstractController.cc +++ b/src/mem/ruby/slicc_interface/AbstractController.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 ARM Limited + * Copyright (c) 2017,2019 ARM Limited * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -55,6 +55,7 @@ AbstractController::AbstractController(const Params *p) m_number_of_TBEs(p->number_of_TBEs), m_transitions_per_cycle(p->transitions_per_cycle), m_buffer_size(p->buffer_size), m_recycle_latency(p->recycle_latency), + m_mandatory_queue_latency(p->mandatory_queue_latency), memoryPort(csprintf("%s.memory", name()), this, ""), addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()) { |