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| author | Gabe Black <gabeblack@google.com> | 2019-03-07 03:02:35 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-03-19 10:22:50 +0000 |
| commit | d3d24835bcc03ecf312ac6ba7df114656770730f (patch) | |
| tree | 43bb564a7bc3e22ffd7b1b906f6f96742ecb619a /src/mem/ruby/slicc_interface/AbstractController.hh | |
| parent | 378d9ccbeb4053aeeab002159b26625854af54f7 (diff) | |
| download | gem5-d3d24835bcc03ecf312ac6ba7df114656770730f.tar.xz | |
arch, cpu, dev, gpu, mem, sim, python: start using getPort.
Replace the getMasterPort, getSlavePort, and getEthPort functions
with getPort, and remove extraneous mechanisms that are no longer
necessary.
Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/mem/ruby/slicc_interface/AbstractController.hh')
| -rw-r--r-- | src/mem/ruby/slicc_interface/AbstractController.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh index 35cd3d2a5..5e39a28d2 100644 --- a/src/mem/ruby/slicc_interface/AbstractController.hh +++ b/src/mem/ruby/slicc_interface/AbstractController.hh @@ -126,8 +126,8 @@ class AbstractController : public MemObject, public Consumer virtual void initNetQueues() = 0; /** A function used to return the port associated with this bus object. */ - BaseMasterPort& getMasterPort(const std::string& if_name, - PortID idx = InvalidPortID); + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID); void queueMemoryRead(const MachineID &id, Addr addr, Cycles latency); void queueMemoryWrite(const MachineID &id, Addr addr, Cycles latency, |