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author | Andreas Hansson <andreas.hansson@arm.com> | 2014-10-16 05:49:43 -0400 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-10-16 05:49:43 -0400 |
commit | df973abef3a70074971375cfe52c46f53528c00e (patch) | |
tree | 7c10603edb5c66631288cb0f9fa334df4cf3d8a9 /src/mem/ruby/structures/RubyPrefetcher.py | |
parent | 37908d62a4b45962a6e6f5993027b6b9bafa296d (diff) | |
download | gem5-df973abef3a70074971375cfe52c46f53528c00e.tar.xz |
mem: Dynamically determine page bytes in memory components
This patch takes a step towards an ISA-agnostic memory
system by enabling the components to establish the page size after
instantiation. The swap operation in the memory is now also allowing
any granularity to avoid depending on the IntReg of the ISA.
Diffstat (limited to 'src/mem/ruby/structures/RubyPrefetcher.py')
-rw-r--r-- | src/mem/ruby/structures/RubyPrefetcher.py | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mem/ruby/structures/RubyPrefetcher.py b/src/mem/ruby/structures/RubyPrefetcher.py index a02b11696..18bb3dc69 100644 --- a/src/mem/ruby/structures/RubyPrefetcher.py +++ b/src/mem/ruby/structures/RubyPrefetcher.py @@ -27,7 +27,9 @@ # Authors: Nilay Vaish from m5.SimObject import SimObject +from System import System from m5.params import * +from m5.proxy import * class Prefetcher(SimObject): type = 'Prefetcher' @@ -45,3 +47,4 @@ class Prefetcher(SimObject): num_startup_pfs = Param.UInt32(1, "") cross_page = Param.Bool(False, """True if prefetched address can be on a page different from the observed address""") + sys = Param.System(Parent.any, "System this prefetcher belongs to") |