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| author | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-08-20 11:46:12 -0700 |
|---|---|---|
| committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-08-20 11:46:12 -0700 |
| commit | 8e5c441a54b481085d6311f14af66e41b5766f91 (patch) | |
| tree | 8d0e6f8395685fb8a7fb2eda83e572301e687d1a /src/mem/ruby/system/CacheMemory.cc | |
| parent | 54d76f0ce5d721ad3b4de168db98054844e634cc (diff) | |
| download | gem5-8e5c441a54b481085d6311f14af66e41b5766f91.tar.xz | |
ruby: fix ruby llsc support to sync sc outcomes
Added support so that ruby can determine the outcome of store conditional
operations and reflect that outcome to M5 physical memory and cpus.
Diffstat (limited to 'src/mem/ruby/system/CacheMemory.cc')
| -rw-r--r-- | src/mem/ruby/system/CacheMemory.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mem/ruby/system/CacheMemory.cc b/src/mem/ruby/system/CacheMemory.cc index 9102d1963..604113238 100644 --- a/src/mem/ruby/system/CacheMemory.cc +++ b/src/mem/ruby/system/CacheMemory.cc @@ -353,7 +353,9 @@ CacheMemory::changePermission(const Address& address, lookup(address).m_Permission = new_perm; Index cacheSet = addressToCacheSet(address); int loc = findTagInSet(cacheSet, address); - if (new_perm != AccessPermission_Read_Write) { + if ((new_perm == AccessPermission_Invalid) || + (new_perm == AccessPermission_NotPresent) || + (new_perm == AccessPermission_Stale)) { DPRINTF(RubyCache, "Permission clearing lock for addr: %x\n", address); m_locked[cacheSet][loc] = -1; } |