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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-01-11 13:39:58 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-01-11 13:39:58 -0600 |
| commit | 2d3cae02f5d4a6c1f116f922d0ee3dde9e9dcc77 (patch) | |
| tree | 549c4b9634a6ed2bf1fbd8914122615b2f89d618 /src/mem/ruby/system/RubyPort.hh | |
| parent | 17fc60ee88cf6cc6d0e703e04a90951f77cf48da (diff) | |
| download | gem5-2d3cae02f5d4a6c1f116f922d0ee3dde9e9dcc77.tar.xz | |
Ruby Port: Add a list of cpu ports attached to this port
Diffstat (limited to 'src/mem/ruby/system/RubyPort.hh')
| -rw-r--r-- | src/mem/ruby/system/RubyPort.hh | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh index 88e865766..0160d8fc8 100644 --- a/src/mem/ruby/system/RubyPort.hh +++ b/src/mem/ruby/system/RubyPort.hh @@ -148,6 +148,10 @@ class RubyPort : public MemObject M5Port* physMemPort; + /*! Vector of CPU Port attached to this Ruby port. */ + typedef std::vector<M5Port*>::iterator CpuPortIter; + std::vector<M5Port*> cpu_ports; + PhysicalMemory* physmem; RubySystem* ruby_system; |