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author | Lisa Hsu <Lisa.Hsu@amd.com> | 2011-03-31 17:17:57 -0700 |
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committer | Lisa Hsu <Lisa.Hsu@amd.com> | 2011-03-31 17:17:57 -0700 |
commit | 322b9ca2c5b0465db7086abdc6eadca061932575 (patch) | |
tree | b14837962707de7b90b95c0b0a7b09ffa1988847 /src/mem/ruby/system/SConscript | |
parent | 06fcaf9104cefe5a2c0062b9357dae46bfd9992a (diff) | |
download | gem5-322b9ca2c5b0465db7086abdc6eadca061932575.tar.xz |
Ruby: Add new object called WireBuffer to mimic a Wire.
This is a substitute for MessageBuffers between controllers where you don't
want messages to actually go through the Network, because requests/responses can
always get reordered wrt to one another (even if you turn off Randomization and turn on Ordered)
because you are, after all, going through a network with contention. For systems where you model
multiple controllers that are very tightly coupled and do not actually go through a network,
it is a pain to have to write a coherence protocol to account for mixed up request/response orderings
despite the fact that it's completely unrealistic. This is *not* meant as a substitute for real
MessageBuffers when messages do in fact go over a network.
Diffstat (limited to 'src/mem/ruby/system/SConscript')
-rw-r--r-- | src/mem/ruby/system/SConscript | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mem/ruby/system/SConscript b/src/mem/ruby/system/SConscript index edc9d451f..f1e7c425c 100644 --- a/src/mem/ruby/system/SConscript +++ b/src/mem/ruby/system/SConscript @@ -37,6 +37,7 @@ SimObject('Cache.py') SimObject('Sequencer.py') SimObject('DirectoryMemory.py') SimObject('MemoryControl.py') +SimObject('WireBuffer.py') SimObject('RubySystem.py') Source('DMASequencer.cc') @@ -44,6 +45,7 @@ Source('DirectoryMemory.cc') Source('SparseMemory.cc') Source('CacheMemory.cc') Source('MemoryControl.cc') +Source('WireBuffer.cc') Source('MemoryNode.cc') Source('PersistentTable.cc') Source('RubyPort.cc') |