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authorNilay Vaish <nilay@cs.wisc.edu>2015-08-14 19:28:43 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2015-08-14 19:28:43 -0500
commit5060e572ca07b98f7d84679bac81c0151dee46b9 (patch)
treed7ff69a0fb7c5959b038dad87cd01e08801f33fe /src/mem/ruby
parentb815221718d246549311b2923a2da7a233e1f625 (diff)
downloadgem5-5060e572ca07b98f7d84679bac81c0151dee46b9.tar.xz
ruby: call setMRU from L1 controllers, not from sequencer
Currently the sequencer calls the function setMRU that updates the replacement policy structures with the first level caches. While functionally this is correct, the problem is that this requires calling findTagInSet() which is an expensive function. This patch removes the calls to setMRU from the sequencer. All controllers should now update the replacement policy on their own. The set and the way index for a given cache entry can be found within the AbstractCacheEntry structure. Use these indicies to update the replacement policy structures.
Diffstat (limited to 'src/mem/ruby')
-rw-r--r--src/mem/ruby/structures/CacheMemory.cc8
-rw-r--r--src/mem/ruby/structures/CacheMemory.hh2
-rw-r--r--src/mem/ruby/system/Sequencer.cc12
3 files changed, 14 insertions, 8 deletions
diff --git a/src/mem/ruby/structures/CacheMemory.cc b/src/mem/ruby/structures/CacheMemory.cc
index ab2647759..931f58a8e 100644
--- a/src/mem/ruby/structures/CacheMemory.cc
+++ b/src/mem/ruby/structures/CacheMemory.cc
@@ -344,6 +344,14 @@ CacheMemory::setMRU(Addr address)
}
void
+CacheMemory::setMRU(const AbstractCacheEntry *e)
+{
+ uint32_t cacheSet = e->getSetIndex();
+ uint32_t loc = e->getWayIndex();
+ m_replacementPolicy_ptr->touch(cacheSet, loc, curTick());
+}
+
+void
CacheMemory::recordCacheContents(int cntrl, CacheRecorder* tr) const
{
uint64_t warmedUpBlocks = 0;
diff --git a/src/mem/ruby/structures/CacheMemory.hh b/src/mem/ruby/structures/CacheMemory.hh
index 1af446950..7ce674e61 100644
--- a/src/mem/ruby/structures/CacheMemory.hh
+++ b/src/mem/ruby/structures/CacheMemory.hh
@@ -106,6 +106,8 @@ class CacheMemory : public SimObject
// Set this address to most recently used
void setMRU(Addr address);
+ // Set this entry to most recently used
+ void setMRU(const AbstractCacheEntry *e);
// Functions for locking and unlocking cache lines corresponding to the
// provided address. These are required for supporting atomic memory
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index b21c70743..740db7d8d 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -496,19 +496,15 @@ Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data,
const Cycles forwardRequestTime,
const Cycles firstResponseTime)
{
+ warn_once("Replacement policy updates recently became the responsibility "
+ "of SLICC state machines. Make sure to setMRU() near callbacks "
+ "in .sm files!");
+
PacketPtr pkt = srequest->pkt;
Addr request_address(pkt->getAddr());
- Addr request_line_address = makeLineAddress(pkt->getAddr());
RubyRequestType type = srequest->m_type;
Cycles issued_time = srequest->issue_time;
- // Set this cache entry to the most recently used
- if (type == RubyRequestType_IFETCH) {
- m_instCache_ptr->setMRU(request_line_address);
- } else {
- m_dataCache_ptr->setMRU(request_line_address);
- }
-
assert(curCycle() >= issued_time);
Cycles total_latency = curCycle() - issued_time;