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authorAlexandru <alexandru.dutu@amd.com>2014-04-01 12:18:12 -0500
committerAlexandru <alexandru.dutu@amd.com>2014-04-01 12:18:12 -0500
commit26ac28dec288e4fd96d999267ec7cafad4d58c5a (patch)
tree937c3fc79a1d4622215c0e23ac6ae6e5945aab68 /src/mem/se_translating_port_proxy.hh
parent6dc90da08f5e743111ab9ae2623d5c0dad808d29 (diff)
downloadgem5-26ac28dec288e4fd96d999267ec7cafad4d58c5a.tar.xz
mem: adding a multi-level page table class
This patch defines a multi-level page table class that stores the page table in system memory, consistent with ISA specifications. In this way, cpu models that use the actual hardware to execute (e.g. KvmCPU), are able to traverse the page table.
Diffstat (limited to 'src/mem/se_translating_port_proxy.hh')
-rw-r--r--src/mem/se_translating_port_proxy.hh2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/se_translating_port_proxy.hh b/src/mem/se_translating_port_proxy.hh
index c0e522611..99973a6e9 100644
--- a/src/mem/se_translating_port_proxy.hh
+++ b/src/mem/se_translating_port_proxy.hh
@@ -75,7 +75,7 @@ class SETranslatingPortProxy : public PortProxy
};
private:
- PageTable *pTable;
+ PageTableBase *pTable;
Process *process;
AllocType allocating;