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| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-25 13:14:44 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-25 13:14:44 -0400 |
| commit | 6f6adbf0f6a4ca96cf44a24ea575860af56eb7b2 (patch) | |
| tree | dfaacd19e7e947149b52b7d5d55fe069ed7aede0 /src/mem | |
| parent | 8fe556338db4cc50a3f1ba20306bc5e464941f2b (diff) | |
| download | gem5-6f6adbf0f6a4ca96cf44a24ea575860af56eb7b2.tar.xz | |
dev: Make default clock more reasonable for system and devices
This patch changes the default system clock from 1THz to 1GHz. This
clock is used by all modules that do not override the default (parent
clock), and primarily affects the IO subsystem. Every DMA device uses
its clock to schedule the next transfer, and the change will thus
cause this inter-transfer delay to be longer.
The default clock of the bus is removed, as the clock inherited from
the system provides exactly the same value.
A follow-on patch will bump the stats.
Diffstat (limited to 'src/mem')
| -rw-r--r-- | src/mem/Bus.py | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mem/Bus.py b/src/mem/Bus.py index 447fc723e..45b1f1b0a 100644 --- a/src/mem/Bus.py +++ b/src/mem/Bus.py @@ -47,8 +47,6 @@ class BaseBus(MemObject): abstract = True slave = VectorSlavePort("vector port for connecting masters") master = VectorMasterPort("vector port for connecting slaves") - # Override the default clock - clock = '1GHz' header_cycles = Param.Cycles(1, "cycles of overhead per transaction") width = Param.Unsigned(8, "bus width (bytes)") block_size = Param.Unsigned(64, "The default block size if not set by " \ |