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| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-06-22 21:29:43 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-06-22 21:29:43 -0700 |
| commit | de2321de81506a81f64641babe0bce17ab946b9c (patch) | |
| tree | 06f73c0335b9a743faaa79b5465afe167a376f58 /src/mem | |
| parent | 96767fc7210e952d5874433b7f79a055c9bd692d (diff) | |
| download | gem5-de2321de81506a81f64641babe0bce17ab946b9c.tar.xz | |
cache: fix longstanding prefetcher bug
Thanks to Joe Gross for pointing this out (again?).
Apologies to anyone who pointed it out earlier and
we didn't listen.
Diffstat (limited to 'src/mem')
| -rw-r--r-- | src/mem/cache/cache_impl.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index d5eb38e48..8ff11b26f 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -1308,7 +1308,7 @@ Cache<TagStore>::getNextMSHR() // fall through... no pending requests. Try a prefetch. assert(!miss_mshr && !write_mshr); - if (!mshrQueue.isFull()) { + if (prefetcher && !mshrQueue.isFull()) { // If we have a miss queue slot, we can try a prefetch PacketPtr pkt = prefetcher->getPacket(); if (pkt) { |