diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2006-10-20 16:39:47 -0400 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-10-20 16:39:47 -0400 |
| commit | 0b5cf4ba6eb2702ade2bc77c07842edd97eab264 (patch) | |
| tree | 4e1ed8130794049e771759059269e6dc23848180 /src/python/m5/objects | |
| parent | 76c07ea46bc4f8f6d500f909abfb07addf217940 (diff) | |
| parent | 6c6b78126a38cf92eef89f027312e1c7a063bd18 (diff) | |
| download | gem5-0b5cf4ba6eb2702ade2bc77c07842edd97eab264.tar.xz | |
Merge zizzer.eecs.umich.edu:/bk/newmem
into zeep.eecs.umich.edu:/home/gblack/m5/newmem
--HG--
extra : convert_revision : 2711fec2bf72801999b060e65f0bf744c18734fb
Diffstat (limited to 'src/python/m5/objects')
| -rw-r--r-- | src/python/m5/objects/AlphaConsole.py | 2 | ||||
| -rw-r--r-- | src/python/m5/objects/BaseCache.py | 1 | ||||
| -rw-r--r-- | src/python/m5/objects/IntrControl.py | 2 | ||||
| -rw-r--r-- | src/python/m5/objects/MemTest.py | 1 |
4 files changed, 3 insertions, 3 deletions
diff --git a/src/python/m5/objects/AlphaConsole.py b/src/python/m5/objects/AlphaConsole.py index 1c71493b1..f968aaa40 100644 --- a/src/python/m5/objects/AlphaConsole.py +++ b/src/python/m5/objects/AlphaConsole.py @@ -4,7 +4,7 @@ from Device import BasicPioDevice class AlphaConsole(BasicPioDevice): type = 'AlphaConsole' - cpu = Param.BaseCPU(Parent.any, "Processor") + cpu = Param.BaseCPU(Parent.cpu[0], "Processor") disk = Param.SimpleDisk("Simple Disk") sim_console = Param.SimConsole(Parent.any, "The Simulator Console") system = Param.AlphaSystem(Parent.any, "system object") diff --git a/src/python/m5/objects/BaseCache.py b/src/python/m5/objects/BaseCache.py index db58a177f..773a11bea 100644 --- a/src/python/m5/objects/BaseCache.py +++ b/src/python/m5/objects/BaseCache.py @@ -14,7 +14,6 @@ class BaseCache(MemObject): "This cache connects to a compressed memory") compression_latency = Param.Latency('0ns', "Latency in cycles of compression algorithm") - do_copy = Param.Bool(False, "perform fast copies in the cache") hash_delay = Param.Int(1, "time in cycles of hash access") lifo = Param.Bool(False, "whether this NIC partition should use LIFO repl. policy") diff --git a/src/python/m5/objects/IntrControl.py b/src/python/m5/objects/IntrControl.py index 95be0f4df..a7cf5cc84 100644 --- a/src/python/m5/objects/IntrControl.py +++ b/src/python/m5/objects/IntrControl.py @@ -3,4 +3,4 @@ from m5.params import * from m5.proxy import * class IntrControl(SimObject): type = 'IntrControl' - cpu = Param.BaseCPU(Parent.any, "the cpu") + cpu = Param.BaseCPU(Parent.cpu[0], "the cpu") diff --git a/src/python/m5/objects/MemTest.py b/src/python/m5/objects/MemTest.py index 83399be80..1219ddd4d 100644 --- a/src/python/m5/objects/MemTest.py +++ b/src/python/m5/objects/MemTest.py @@ -13,6 +13,7 @@ class MemTest(SimObject): percent_reads = Param.Percent(65, "target read percentage") percent_source_unaligned = Param.Percent(50, "percent of copy source address that are unaligned") + percent_functional = Param.Percent(50, "percent of access that are functional") percent_uncacheable = Param.Percent(10, "target uncacheable percentage") progress_interval = Param.Counter(1000000, |