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| author | Kevin Lim <ktlim@umich.edu> | 2006-07-11 13:43:30 -0400 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2006-07-11 13:43:30 -0400 |
| commit | 0b0cb2bca71acdab4a30acc639509030631f9dfd (patch) | |
| tree | fee4bbd0c1bfb45b7abec14e944400852f90b468 /src/python/m5/objects | |
| parent | b55cda163ed1a29ee5e08cde36743047923ab475 (diff) | |
| parent | 7078d8d1b42c1a158c854b3e07800f20aa695bfb (diff) | |
| download | gem5-0b0cb2bca71acdab4a30acc639509030631f9dfd.tar.xz | |
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem
--HG--
extra : convert_revision : c565fd7cebaa4058ba510b3db50a9c76bf301228
Diffstat (limited to 'src/python/m5/objects')
| -rw-r--r-- | src/python/m5/objects/O3CPU.py | 5 | ||||
| -rw-r--r-- | src/python/m5/objects/OzoneCPU.py | 3 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/python/m5/objects/O3CPU.py b/src/python/m5/objects/O3CPU.py index 9ccbdcf53..d6bc454ad 100644 --- a/src/python/m5/objects/O3CPU.py +++ b/src/python/m5/objects/O3CPU.py @@ -10,6 +10,8 @@ class DerivO3CPU(BaseCPU): checker = Param.BaseCPU(NULL, "checker") cachePorts = Param.Unsigned("Cache Ports") + icache_port = Port("Instruction Port") + dcache_port = Port("Data Port") decodeToFetchDelay = Param.Unsigned("Decode to fetch delay") renameToFetchDelay = Param.Unsigned("Rename to fetch delay") @@ -51,6 +53,9 @@ class DerivO3CPU(BaseCPU): trapLatency = Param.Tick("Trap latency") fetchTrapLatency = Param.Tick("Fetch trap latency") + backComSize = Param.Unsigned("Time buffer size for backwards communication") + forwardComSize = Param.Unsigned("Time buffer size for forward communication") + predType = Param.String("Branch predictor type ('local', 'tournament')") localPredictorSize = Param.Unsigned("Size of local predictor") localCtrBits = Param.Unsigned("Bits per counter") diff --git a/src/python/m5/objects/OzoneCPU.py b/src/python/m5/objects/OzoneCPU.py index 8aff89203..88fb63c74 100644 --- a/src/python/m5/objects/OzoneCPU.py +++ b/src/python/m5/objects/OzoneCPU.py @@ -9,6 +9,9 @@ class DerivOzoneCPU(BaseCPU): checker = Param.BaseCPU("Checker CPU") + icache_port = Port("Instruction Port") + dcache_port = Port("Data Port") + width = Param.Unsigned("Width") frontEndWidth = Param.Unsigned("Front end width") backEndWidth = Param.Unsigned("Back end width") |