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| author | Alexandru Dutu <alexandru.dutu@amd.com> | 2014-11-23 18:01:09 -0800 |
|---|---|---|
| committer | Alexandru Dutu <alexandru.dutu@amd.com> | 2014-11-23 18:01:09 -0800 |
| commit | 1f539f13c32ad5a9187d56a098d4c857639b0e05 (patch) | |
| tree | 7618c3b946d9c25d9b22018f226eee77b6de4aaf /src/sim/Process.py | |
| parent | c11bcb8119273ef91c40a25b8fd9471a887d0ee5 (diff) | |
| download | gem5-1f539f13c32ad5a9187d56a098d4c857639b0e05.tar.xz | |
mem: Page Table map api modification
This patch adds uncacheable/cacheable and read-only/read-write attributes to
the map method of PageTableBase. It also modifies the constructor of TlbEntry
structs for all architectures to consider the new attributes.
Diffstat (limited to 'src/sim/Process.py')
| -rw-r--r-- | src/sim/Process.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/sim/Process.py b/src/sim/Process.py index f64ab0883..ca9aaf5b1 100644 --- a/src/sim/Process.py +++ b/src/sim/Process.py @@ -45,7 +45,7 @@ class Process(SimObject): @classmethod def export_methods(cls, code): - code('bool map(Addr vaddr, Addr paddr, int size);') + code('bool map(Addr vaddr, Addr paddr, int size, bool cacheable=true);') class EmulatedDriver(SimObject): type = 'EmulatedDriver' |