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| author | Gabe Black <gblack@eecs.umich.edu> | 2008-09-03 00:52:54 -0400 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2008-09-03 00:52:54 -0400 |
| commit | 30bc897613a1ee36ed887eb9da1579bd9828186e (patch) | |
| tree | 006078148f05ab1c6e868f482ea9a82a8efea9ea /src | |
| parent | 4aa017affc53b3b730219d3b617f0e237c57debc (diff) | |
| download | gem5-30bc897613a1ee36ed887eb9da1579bd9828186e.tar.xz | |
X86: Fix the microcode for sign/zero extending moves that use high byte registers.
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/x86/isa/insts/general_purpose/data_transfer/move.py | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py index d9a83dfde..35f0436f5 100644 --- a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py +++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py @@ -126,7 +126,8 @@ def macroop MOVSXD_R_P { }; def macroop MOVSX_B_R_R { - sexti reg, regm, 7 + mov t1, t1, regm, dataSize=1 + sexti reg, t1, 7 }; def macroop MOVSX_B_R_M { @@ -160,7 +161,8 @@ def macroop MOVSX_W_R_P { # def macroop MOVZX_B_R_R { - zexti reg, regm, 7 + mov t1, t1, regm, dataSize=1 + zexti reg, t1, 7 }; def macroop MOVZX_B_R_M { |