diff options
| author | Neha Agarwal <neha.agarwal@arm.com> | 2013-11-01 11:56:21 -0400 |
|---|---|---|
| committer | Neha Agarwal <neha.agarwal@arm.com> | 2013-11-01 11:56:21 -0400 |
| commit | 7645c8e611b5530b82789246b5025558f4b1a422 (patch) | |
| tree | f6ce24ca4d5dc02e04b0a71a9045f5ffc7e23645 /src | |
| parent | 10e8978ec0ee7a7443247d7a85ab0b3587740f1a (diff) | |
| download | gem5-7645c8e611b5530b82789246b5025558f4b1a422.tar.xz | |
mem: Fix for 100% write threshold in DRAM controller
This patch fixes the controller when a write threshold of 100% is
used. Earlier for 100% write threshold no data is written to memory
as writes never get triggered since this corner case is not
considered.
Diffstat (limited to 'src')
| -rw-r--r-- | src/mem/simple_dram.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/simple_dram.cc b/src/mem/simple_dram.cc index 9cbca6a1c..9669c7a03 100644 --- a/src/mem/simple_dram.cc +++ b/src/mem/simple_dram.cc @@ -563,7 +563,7 @@ SimpleDRAM::addToWriteQueue(PacketPtr pkt, unsigned int pktCount) accessAndRespond(pkt, frontendLatency); // If your write buffer is starting to fill up, drain it! - if (writeQueue.size() > writeThreshold && !stopReads){ + if (writeQueue.size() >= writeThreshold && !stopReads){ triggerWrites(); } } |