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author | Gabe Black <gblack@eecs.umich.edu> | 2006-10-09 19:35:53 -0400 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2006-10-09 19:35:53 -0400 |
commit | 843888c489c3337a041098a94fc2105359a74a9a (patch) | |
tree | 226ed517a2173b9db2736f188990b0c8fe3f04ca /src | |
parent | a23c6a719323f2ac74cadd3b04c84f3dc679c26e (diff) | |
parent | 9356bcda7b50ae8916eee2dfbad84ed3ea873c1e (diff) | |
download | gem5-843888c489c3337a041098a94fc2105359a74a9a.tar.xz |
Merge zizzer.eecs.umich.edu:/bk/newmem
into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
--HG--
extra : convert_revision : 2adde42edead2cedeeba60cc0d2697a2d58682be
Diffstat (limited to 'src')
-rw-r--r-- | src/cpu/memtest/memtest.cc | 7 | ||||
-rw-r--r-- | src/cpu/memtest/memtest.hh | 2 | ||||
-rw-r--r-- | src/mem/cache/base_cache.cc | 5 | ||||
-rw-r--r-- | src/mem/cache/cache_impl.hh | 18 | ||||
-rw-r--r-- | src/mem/cache/coherence/coherence_protocol.cc | 2 | ||||
-rw-r--r-- | src/mem/packet.hh | 3 |
6 files changed, 22 insertions, 15 deletions
diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc index 609a07a8e..127cad414 100644 --- a/src/cpu/memtest/memtest.cc +++ b/src/cpu/memtest/memtest.cc @@ -71,7 +71,8 @@ MemTest::CpuPort::recvAtomic(Packet *pkt) void MemTest::CpuPort::recvFunctional(Packet *pkt) { - memtest->completeRequest(pkt); + //Do nothing if we see one come through + return; } void @@ -325,7 +326,7 @@ MemTest::tick() } else { paddr = ((base) ? baseAddr1 : baseAddr2) + offset; } - // bool probe = (random() % 2 == 1) && !req->isUncacheable(); + //bool probe = (random() % 2 == 1) && !req->isUncacheable(); bool probe = false; paddr &= ~((1 << access_size) - 1); @@ -364,7 +365,7 @@ MemTest::tick() if (probe) { cachePort.sendFunctional(pkt); -// completeRequest(pkt, result); + completeRequest(pkt); } else { // req->completionEvent = new MemCompleteEvent(req, result, this); if (!cachePort.sendTiming(pkt)) { diff --git a/src/cpu/memtest/memtest.hh b/src/cpu/memtest/memtest.hh index 278012eba..87ecc6de3 100644 --- a/src/cpu/memtest/memtest.hh +++ b/src/cpu/memtest/memtest.hh @@ -113,7 +113,7 @@ class MemTest : public MemObject virtual void getDeviceAddressRanges(AddrRangeList &resp, AddrRangeList &snoop) - { resp.clear(); snoop.clear(); } + { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,-1)); } }; CpuPort cachePort; diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc index b2c3a0439..c56f48eeb 100644 --- a/src/mem/cache/base_cache.cc +++ b/src/mem/cache/base_cache.cc @@ -216,7 +216,10 @@ BaseCache::CacheEvent::process() } //Response //Know the packet to send - pkt->result = Packet::Success; + if (pkt->flags & NACKED_LINE) + pkt->result = Packet::Nacked; + else + pkt->result = Packet::Success; pkt->makeTimingResponse(); if (!cachePort->drainList.empty()) { //Already blocked waiting for bus, just append diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index bde7ac04b..c3c1c0881 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -63,9 +63,8 @@ doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide) if (pkt->isWrite() && (pkt->req->isLocked())) { pkt->req->setScResult(1); } - if (!(pkt->flags & SATISFIED)) { - access(pkt); - } + access(pkt); + } else { @@ -204,9 +203,8 @@ Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt) pkt->getAddr() & (((ULL(1))<<48)-1), pkt->getAddr() & ~((Addr)blkSize - 1)); - //@todo Should this return latency have the hit latency in it? -// respond(pkt,curTick+lat); pkt->flags |= SATISFIED; + //Invalidates/Upgrades need no response if they get the bus // return MA_HIT; //@todo, return values return true; } @@ -306,6 +304,13 @@ Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt) { BlkType *blk = NULL; if (pkt->senderState) { + if (pkt->result == Packet::Nacked) { + pkt->reinitFromRequest(); + panic("Unimplemented NACK of packet\n"); + } + if (pkt->result == Packet::BadAddress) { + //Make the response a Bad address and send it + } // MemDebug::cacheResponse(pkt); DPRINTF(Cache, "Handling reponse to %x, blk addr: %x\n",pkt->getAddr(), pkt->getAddr() & (((ULL(1))<<48)-1)); @@ -392,7 +397,6 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt) assert(!(pkt->flags & SATISFIED)); pkt->flags |= SATISFIED; pkt->flags |= NACKED_LINE; - assert("Don't detect these on the other side yet\n"); respondToSnoop(pkt, curTick + hitLatency); return; } @@ -406,7 +410,7 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt) //@todo Make it so that a read to a pending read can't be exclusive now. //Set the address so find match works - assert("Don't have invalidates yet\n"); + panic("Don't have invalidates yet\n"); invalidatePkt->addrOverride(pkt->getAddr()); //Append the invalidate on diff --git a/src/mem/cache/coherence/coherence_protocol.cc b/src/mem/cache/coherence/coherence_protocol.cc index bcf3ce9c5..e28dda3dc 100644 --- a/src/mem/cache/coherence/coherence_protocol.cc +++ b/src/mem/cache/coherence/coherence_protocol.cc @@ -271,7 +271,7 @@ CoherenceProtocol::CoherenceProtocol(const string &name, } Packet::Command writeToSharedCmd = doUpgrades ? Packet::UpgradeReq : Packet::ReadExReq; - Packet::Command writeToSharedResp = doUpgrades ? Packet::UpgradeResp : Packet::ReadExResp; + Packet::Command writeToSharedResp = doUpgrades ? Packet::UpgradeReq : Packet::ReadExResp; //@todo add in hardware prefetch to this list if (protocol == "msi") { diff --git a/src/mem/packet.hh b/src/mem/packet.hh index 5c513ae7a..4d57aee75 100644 --- a/src/mem/packet.hh +++ b/src/mem/packet.hh @@ -199,8 +199,7 @@ class Packet | NeedsResponse | HasData, InvalidateReq = IsInvalidate | IsRequest, WriteInvalidateReq = IsWrite | IsInvalidate | IsRequest | HasData, - UpgradeReq = IsInvalidate | IsRequest | NeedsResponse, - UpgradeResp = IsInvalidate | IsResponse | NeedsResponse, + UpgradeReq = IsInvalidate | IsRequest, ReadExReq = IsRead | IsInvalidate | IsRequest | NeedsResponse, ReadExResp = IsRead | IsInvalidate | IsResponse | NeedsResponse | HasData |