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authorRon Dreslinski <rdreslin@umich.edu>2006-10-12 13:33:21 -0400
committerRon Dreslinski <rdreslin@umich.edu>2006-10-12 13:33:21 -0400
commitba4c224c390916fb489aa7179655c71d7fca1e13 (patch)
tree6c02f9acfeb257791c30ad995cc75a0d382e94b8 /src
parent78aec04b660544ea7af80d76912b4422c4426602 (diff)
downloadgem5-ba4c224c390916fb489aa7179655c71d7fca1e13.tar.xz
Fix problems with unCacheable addresses in timing-coherence
src/base/traceflags.py: src/mem/physical.cc: Add debug falgs fro physical memory accesses src/mem/cache/cache_impl.hh: Snoops to uncacheable blocks should not happen src/mem/cache/miss/miss_queue.cc: Set the size properly on unCacheable accesses --HG-- extra : convert_revision : fc78192863afb11fc7c591fba169021b9e127d16
Diffstat (limited to 'src')
-rw-r--r--src/base/traceflags.py1
-rw-r--r--src/mem/cache/cache_impl.hh5
-rw-r--r--src/mem/cache/miss/miss_queue.cc2
-rw-r--r--src/mem/physical.cc4
4 files changed, 11 insertions, 1 deletions
diff --git a/src/base/traceflags.py b/src/base/traceflags.py
index f871ce35f..c05f9e5b0 100644
--- a/src/base/traceflags.py
+++ b/src/base/traceflags.py
@@ -122,6 +122,7 @@ baseFlags = [
'MSHR',
'Mbox',
'MemDepUnit',
+ 'MemoryAccess',
'O3CPU',
'OzoneCPU',
'OzoneLSQ',
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index a68418f24..150abbe52 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -389,6 +389,11 @@ template<class TagStore, class Buffering, class Coherence>
void
Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
{
+ if (pkt->req->isUncacheable()) {
+ //Can't get a hit on an uncacheable address
+ //Revisit this for multi level coherence
+ return;
+ }
Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
BlkType *blk = tags->findBlock(pkt);
MSHR *mshr = missQueue->findMSHR(blk_addr);
diff --git a/src/mem/cache/miss/miss_queue.cc b/src/mem/cache/miss/miss_queue.cc
index c7b0e0890..c23b542f5 100644
--- a/src/mem/cache/miss/miss_queue.cc
+++ b/src/mem/cache/miss/miss_queue.cc
@@ -352,7 +352,7 @@ MissQueue::setPrefetcher(BasePrefetcher *_prefetcher)
MSHR*
MissQueue::allocateMiss(Packet * &pkt, int size, Tick time)
{
- MSHR* mshr = mq.allocate(pkt, blkSize);
+ MSHR* mshr = mq.allocate(pkt, size);
mshr->order = order++;
if (!pkt->req->isUncacheable() ){//&& !pkt->isNoAllocate()) {
// Mark this as a cache line fill
diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index 7303f278e..f5a0ade15 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -201,12 +201,16 @@ PhysicalMemory::doFunctionalAccess(Packet *pkt)
if (pkt->req->isLocked()) {
trackLoadLocked(pkt->req);
}
+ DPRINTF(MemoryAccess, "Performing Read of size %i on address 0x%x\n",
+ pkt->getSize(), pkt->getAddr());
memcpy(pkt->getPtr<uint8_t>(),
pmemAddr + pkt->getAddr() - params()->addrRange.start,
pkt->getSize());
}
else if (pkt->isWrite()) {
if (writeOK(pkt->req)) {
+ DPRINTF(MemoryAccess, "Performing Write of size %i on address 0x%x\n",
+ pkt->getSize(), pkt->getAddr());
memcpy(pmemAddr + pkt->getAddr() - params()->addrRange.start,
pkt->getPtr<uint8_t>(), pkt->getSize());
}