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authorNikos Nikoleris <nikos.nikoleris@arm.com>2017-12-19 16:58:33 +0000
committerNikos Nikoleris <nikos.nikoleris@arm.com>2018-02-07 16:14:39 +0000
commitf4e27c3ff56894e738bd2a975646b5a07d9ea75c (patch)
tree7ed54c037502d2b97fb4a6eaaca46be18468f0f2 /src
parentb72d69c5caa382902fc200086e861e92ef883163 (diff)
downloadgem5-f4e27c3ff56894e738bd2a975646b5a07d9ea75c.tar.xz
arch-arm: Fault when dc ivac is executed from EL0
A previous change enabled execution of dc ivac from EL0 when SCTLR_EL1.UCI=1. The Arm ARM specifies that dc ivac is the only data cache maintenance operation by VA that cannot be executed from EL0. This changeset essential reverts the change: 8d43922 arch-arm: Allow dc ivac from EL0 when SCTLR_EL1.UCI=1 Change-Id: Ia25fab13846a151f548e649a16067feb1ff65c9c Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7823 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src')
-rw-r--r--src/arch/arm/miscregs.cc5
1 files changed, 2 insertions, 3 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index a9031fe0e..c0b6aa5d5 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -922,8 +922,7 @@ canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
if (el == EL0 && !sctlr.dze)
return false;
}
- if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt ||
- reg == MISCREG_DC_IVAC_Xt) {
+ if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) {
SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
if (el == EL0 && !sctlr.uci)
return false;
@@ -3557,7 +3556,7 @@ ISA::initializeMiscRegMetadata()
.writes(1).exceptUserMode();
InitReg(MISCREG_DC_IVAC_Xt)
.warnNotFail()
- .writes(1);
+ .writes(1).exceptUserMode();
InitReg(MISCREG_DC_ISW_Xt)
.warnNotFail()
.writes(1).exceptUserMode();