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authorJoel Hestness <hestness@cs.utexas.edu>2010-08-12 17:16:02 -0700
committerJoel Hestness <hestness@cs.utexas.edu>2010-08-12 17:16:02 -0700
commit53c241fc16e4edaae8440b3dd360503537dbaba3 (patch)
tree770f719bfdc90226ba7b755782382a3192513c78 /src
parent2e9e75447a50146e0e8346de4362f7a4570f84ec (diff)
downloadgem5-53c241fc16e4edaae8440b3dd360503537dbaba3.tar.xz
TimingSimpleCPU: fix NO_ACCESS memory op handling
When a request is NO_ACCESS (x86 CDA microinstruction), the memory op doesn't go to the cache, so TimingSimpleCPU::completeDataAccess needs to handle the case where the current status of the CPU is Running and not DcacheWaitResponse or DTBWaitResponse
Diffstat (limited to 'src')
-rw-r--r--src/cpu/simple/timing.cc3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index b8fc5ab84..8a53aac3a 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -868,6 +868,8 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
// received a response from the dcache: complete the load or store
// instruction
assert(!pkt->isError());
+ assert(_status == DcacheWaitResponse || _status == DTBWaitResponse ||
+ pkt->req->getFlags().isSet(Request::NO_ACCESS));
numCycles += tickToCycles(curTick - previousTick);
previousTick = curTick;
@@ -897,7 +899,6 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
}
}
- assert(_status == DcacheWaitResponse || _status == DTBWaitResponse);
_status = Running;
Fault fault = curStaticInst->completeAcc(pkt, this, traceData);