Merge zizzer.eecs.umich.edu:/bk/newmem

into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86

src/cpu/simple/base.cc:
    Hand merge

--HG--
extra : convert_revision : a2902ef9d917d22ffb9c7dfa2fd444694a65240d

88 files changed, 1815 insertions, 665 deletions

diff --git a/src/arch/alpha/AlphaSystem.py b/src/arch/alpha/AlphaSystem.py
new file mode 100644
index 000000000..a19aeb763
--- /dev/null
+++ b/src/arch/alpha/AlphaSystem.py
@@ -0,0 +1,52 @@
+# Copyright (c) 2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+from m5.params import *
+from System import System
+
+class AlphaSystem(System):
+    type = 'AlphaSystem'
+    console = Param.String("file that contains the console code")
+    pal = Param.String("file that contains palcode")
+    system_type = Param.UInt64("Type of system we are emulating")
+    system_rev = Param.UInt64("Revision of system we are emulating")
+
+class LinuxAlphaSystem(AlphaSystem):
+    type = 'LinuxAlphaSystem'
+    system_type = 34
+    system_rev = 1 << 10
+
+class FreebsdAlphaSystem(AlphaSystem):
+    type = 'FreebsdAlphaSystem'
+    system_type = 34
+    system_rev = 1 << 10
+
+class Tru64AlphaSystem(AlphaSystem):
+    type = 'Tru64AlphaSystem'
+    system_type = 12
+    system_rev = 2<<1
diff --git a/src/arch/alpha/AlphaTLB.py b/src/arch/alpha/AlphaTLB.py
new file mode 100644
index 000000000..559516725
--- /dev/null
+++ b/src/arch/alpha/AlphaTLB.py
@@ -0,0 +1,42 @@
+# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+from m5.SimObject import SimObject
+from m5.params import *
+class AlphaTLB(SimObject):
+    type = 'AlphaTLB'
+    abstract = True
+    size = Param.Int("TLB size")
+
+class AlphaDTB(AlphaTLB):
+    type = 'AlphaDTB'
+    size = 64
+
+class AlphaITB(AlphaTLB):
+    type = 'AlphaITB'
+    size = 48
diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript
index 61611e9f6..2d59180c4 100644
--- a/src/arch/alpha/SConscript
+++ b/src/arch/alpha/SConscript
@@ -40,6 +40,9 @@ if env['TARGET_ISA'] == 'alpha':
     Source('remote_gdb.cc')
 
     if env['FULL_SYSTEM']:
+        SimObject('AlphaSystem.py')
+        SimObject('AlphaTLB.py')
+
         Source('arguments.cc')
         Source('ev5.cc')
         Source('idle_event.cc')
diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index e342c79cf..c9dbb8cf2 100644
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -41,6 +41,9 @@ if env['TARGET_ISA'] == 'sparc':
     Source('remote_gdb.cc')
 
     if env['FULL_SYSTEM']:
+        SimObject('SparcSystem.py')
+        SimObject('SparcTLB.py')
+
         Source('arguments.cc')
         Source('pagetable.cc')
         Source('stacktrace.cc')
diff --git a/src/arch/sparc/SparcSystem.py b/src/arch/sparc/SparcSystem.py
new file mode 100644
index 000000000..2e65f640d
--- /dev/null
+++ b/src/arch/sparc/SparcSystem.py
@@ -0,0 +1,74 @@
+# Copyright (c) 2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+from m5.params import *
+
+from PhysicalMemory import *
+from System import System
+
+class SparcSystem(System):
+    type = 'SparcSystem'
+    _rom_base = 0xfff0000000
+    _nvram_base = 0x1f11000000
+    _hypervisor_desc_base = 0x1f12080000
+    _partition_desc_base = 0x1f12000000
+    # ROM for OBP/Reset/Hypervisor
+    rom = Param.PhysicalMemory(
+        PhysicalMemory(range=AddrRange(_rom_base, size='8MB')),
+            "Memory to hold the ROM data")
+    # nvram
+    nvram = Param.PhysicalMemory(
+        PhysicalMemory(range=AddrRange(_nvram_base, size='8kB')),
+        "Memory to hold the nvram data")
+    # hypervisor description
+    hypervisor_desc = Param.PhysicalMemory(
+        PhysicalMemory(range=AddrRange(_hypervisor_desc_base, size='8kB')),
+        "Memory to hold the hypervisor description")
+    # partition description
+    partition_desc = Param.PhysicalMemory(
+        PhysicalMemory(range=AddrRange(_partition_desc_base, size='8kB')),
+        "Memory to hold the partition description")
+
+    reset_addr = Param.Addr(_rom_base, "Address to load ROM at")
+    hypervisor_addr = Param.Addr(Addr('64kB') + _rom_base,
+                                 "Address to load hypervisor at")
+    openboot_addr = Param.Addr(Addr('512kB') + _rom_base,
+                               "Address to load openboot at")
+    nvram_addr = Param.Addr(_nvram_base, "Address to put the nvram")
+    hypervisor_desc_addr = Param.Addr(_hypervisor_desc_base,
+            "Address for the hypervisor description")
+    partition_desc_addr = Param.Addr(_partition_desc_base,
+            "Address for the partition description")
+
+    reset_bin = Param.String("file that contains the reset code")
+    hypervisor_bin = Param.String("file that contains the hypervisor code")
+    openboot_bin = Param.String("file that contains the openboot code")
+    nvram_bin = Param.String("file that contains the contents of nvram")
+    hypervisor_desc_bin = Param.String("file that contains the hypervisor description")
+    partition_desc_bin = Param.String("file that contains the partition description")
+
diff --git a/src/arch/sparc/SparcTLB.py b/src/arch/sparc/SparcTLB.py
new file mode 100644
index 000000000..30e5ebb08
--- /dev/null
+++ b/src/arch/sparc/SparcTLB.py
@@ -0,0 +1,42 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ali Saidi
+
+from m5.SimObject import SimObject
+from m5.params import *
+class SparcTLB(SimObject):
+    type = 'SparcTLB'
+    abstract = True
+    size = Param.Int("TLB size")
+
+class SparcDTB(SparcTLB):
+    type = 'SparcDTB'
+    size = 64
+
+class SparcITB(SparcTLB):
+    type = 'SparcITB'
+    size = 64
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index f511ef454..0300694cc 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -142,27 +142,38 @@ void MiscRegFile::clear()
 
 MiscReg MiscRegFile::readRegNoEffect(int miscReg)
 {
-    switch (miscReg) {
-      case MISCREG_TLB_DATA:
-        /* Package up all the data for the tlb:
-         * 6666555555555544444444443333333333222222222211111111110000000000
-         * 3210987654321098765432109876543210987654321098765432109876543210
-         *   secContext   | priContext    |             |tl|partid|  |||||^hpriv
-         *                                                           ||||^red
-         *                                                           |||^priv
-         *                                                           ||^am
-         *                                                           |^lsuim
-         *                                                           ^lsudm
-         */
-        return bits((uint64_t)hpstate,2,2) |
-               bits((uint64_t)hpstate,5,5) << 1 |
-               bits((uint64_t)pstate,3,2) << 2 |
-               bits((uint64_t)lsuCtrlReg,3,2) << 4 |
-               bits((uint64_t)partId,7,0) << 8 |
-               bits((uint64_t)tl,2,0) << 16 |
-               (uint64_t)priContext << 32 |
-               (uint64_t)secContext << 48;
 
+  // The three miscRegs are moved up from the switch statement
+  // due to more frequent calls.
+
+  if (miscReg == MISCREG_GL)
+    return gl;
+  if (miscReg == MISCREG_CWP)
+    return cwp;
+  if (miscReg == MISCREG_TLB_DATA) {
+    /* Package up all the data for the tlb:
+     * 6666555555555544444444443333333333222222222211111111110000000000
+     * 3210987654321098765432109876543210987654321098765432109876543210
+     *   secContext   | priContext    |             |tl|partid|  |||||^hpriv
+     *                                                           ||||^red
+     *                                                           |||^priv
+     *                                                           ||^am
+     *                                                           |^lsuim
+     *                                                           ^lsudm
+     */
+    return bits((uint64_t)hpstate,2,2) |
+           bits((uint64_t)hpstate,5,5) << 1 |
+           bits((uint64_t)pstate,3,2) << 2 |
+           bits((uint64_t)lsuCtrlReg,3,2) << 4 |
+           bits((uint64_t)partId,7,0) << 8 |
+           bits((uint64_t)tl,2,0) << 16 |
+                (uint64_t)priContext << 32 |
+                (uint64_t)secContext << 48;
+  }
+
+    switch (miscReg) {
+      //case MISCREG_TLB_DATA:
+      //  [original contents see above]
       //case MISCREG_Y:
       //  return y;
       //case MISCREG_CCR:
@@ -207,8 +218,9 @@ MiscReg MiscRegFile::readRegNoEffect(int miscReg)
         return tl;
       case MISCREG_PIL:
         return pil;
-      case MISCREG_CWP:
-        return cwp;
+      //CWP, GL moved
+      //case MISCREG_CWP:
+      //  return cwp;
       //case MISCREG_CANSAVE:
       //  return cansave;
       //case MISCREG_CANRESTORE:
@@ -219,8 +231,8 @@ MiscReg MiscRegFile::readRegNoEffect(int miscReg)
       //  return otherwin;
       //case MISCREG_WSTATE:
       //  return wstate;
-      case MISCREG_GL:
-        return gl;
+      //case MISCREG_GL:
+      //  return gl;
 
         /** Hyper privileged registers */
       case MISCREG_HPSTATE:
diff --git a/src/base/loader/elf_object.cc b/src/base/loader/elf_object.cc
index 8f157da28..f76ea593b 100644
--- a/src/base/loader/elf_object.cc
+++ b/src/base/loader/elf_object.cc
@@ -31,23 +31,14 @@
 
 #include <string>
 
-// Because of the -Wundef flag we have to do this
-#define __LIBELF_INTERNAL__     0
-#define __LIBELF_NEED_LINK_H    0
-#define __LIBELF_SYMBOL_VERSIONS 0
-
 #include "gelf.h"
 
 #include "base/loader/elf_object.hh"
-#include "base/misc.hh"
-
 #include "base/loader/symtab.hh"
-
+#include "base/misc.hh"
 #include "base/trace.hh"	// for DPRINTF
-
 #include "sim/byteswap.hh"
 
-
 using namespace std;
 
 ObjectFile *
diff --git a/src/python/m5/objects/BaseCPU.py b/src/cpu/BaseCPU.py
index 986220c3f..6c2aace51 100644
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -1,12 +1,45 @@
+# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
 from m5 import build_env
-from AlphaTLB import AlphaDTB, AlphaITB
-from SparcTLB import SparcDTB, SparcITB
 from Bus import Bus
 import sys
 
+if build_env['FULL_SYSTEM']:
+    if build_env['TARGET_ISA'] == 'alpha':
+        from AlphaTLB import AlphaDTB, AlphaITB
+
+    if build_env['TARGET_ISA'] == 'sparc':
+        from SparcTLB import SparcDTB, SparcITB
+
 class BaseCPU(SimObject):
     type = 'BaseCPU'
     abstract = True
diff --git a/src/cpu/FuncUnit.py b/src/cpu/FuncUnit.py
new file mode 100644
index 000000000..541bdbd83
--- /dev/null
+++ b/src/cpu/FuncUnit.py
@@ -0,0 +1,46 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Kevin Lim
+
+from m5.SimObject import SimObject
+from m5.params import *
+
+class OpType(Enum):
+    vals = ['(null)', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd',
+            'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatDiv', 'FloatSqrt',
+            'MemRead', 'MemWrite', 'IprAccess', 'InstPrefetch']
+
+class OpDesc(SimObject):
+    type = 'OpDesc'
+    issueLat = Param.Int(1, "cycles until another can be issued")
+    opClass = Param.OpType("type of operation")
+    opLat = Param.Int(1, "cycles until result is available")
+
+class FUDesc(SimObject):
+    type = 'FUDesc'
+    count = Param.Int("number of these FU's available")
+    opList = VectorParam.OpDesc("operation classes for this FU type")
diff --git a/src/cpu/IntrControl.py b/src/cpu/IntrControl.py
new file mode 100644
index 000000000..eb4b1696b
--- /dev/null
+++ b/src/cpu/IntrControl.py
@@ -0,0 +1,34 @@
+# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
+class IntrControl(SimObject):
+    type = 'IntrControl'
+    sys = Param.System(Parent.any, "the system we are part of")
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index 1c2278f6f..cce13a072 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -103,6 +103,9 @@ env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS']))
 # and one of these are not being used.
 CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU']
 
+SimObject('BaseCPU.py')
+SimObject('FuncUnit.py')
+
 Source('activity.cc')
 Source('base.cc')
 Source('cpuevent.cc')
@@ -116,6 +119,8 @@ Source('simple_thread.cc')
 Source('thread_state.cc')
 
 if env['FULL_SYSTEM']:
+    SimObject('IntrControl.py')
+
     Source('intr_control.cc')
     Source('profile.cc')
 
diff --git a/src/cpu/memtest/MemTest.py b/src/cpu/memtest/MemTest.py
new file mode 100644
index 000000000..381519972
--- /dev/null
+++ b/src/cpu/memtest/MemTest.py
@@ -0,0 +1,52 @@
+# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
+from m5 import build_env
+
+class MemTest(SimObject):
+    type = 'MemTest'
+    max_loads = Param.Counter("number of loads to execute")
+    atomic = Param.Bool(False, "Execute tester in atomic mode? (or timing)\n")
+    memory_size = Param.Int(65536, "memory size")
+    percent_dest_unaligned = Param.Percent(50,
+        "percent of copy dest address that are unaligned")
+    percent_reads = Param.Percent(65, "target read percentage")
+    percent_source_unaligned = Param.Percent(50,
+        "percent of copy source address that are unaligned")
+    percent_functional = Param.Percent(50, "percent of access that are functional")
+    percent_uncacheable = Param.Percent(10,
+        "target uncacheable percentage")
+    progress_interval = Param.Counter(1000000,
+        "progress report interval (in accesses)")
+    trace_addr = Param.Addr(0, "address to trace")
+
+    test = Port("Port to the memory system to test")
+    functional = Port("Port to the functional memory used for verification")
diff --git a/src/cpu/memtest/SConscript b/src/cpu/memtest/SConscript
index 7b4d6d2c5..1f6621a4c 100644
--- a/src/cpu/memtest/SConscript
+++ b/src/cpu/memtest/SConscript
@@ -31,4 +31,6 @@
 Import('*')
 
 if 'O3CPU' in env['CPU_MODELS']:
+    SimObject('MemTest.py')
+
     Source('memtest.cc')
diff --git a/src/cpu/o3/FUPool.py b/src/cpu/o3/FUPool.py
new file mode 100644
index 000000000..4f07f9867
--- /dev/null
+++ b/src/cpu/o3/FUPool.py
@@ -0,0 +1,40 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Kevin Lim
+
+from m5.SimObject import SimObject
+from m5.params import *
+from FuncUnit import *
+from FuncUnitConfig import *
+
+class FUPool(SimObject):
+    type = 'FUPool'
+    FUList = VectorParam.FUDesc("list of FU's for this pool")
+
+class DefaultFUPool(FUPool):
+    FUList = [ IntALU(), IntMultDiv(), FP_ALU(), FP_MultDiv(), ReadPort(),
+               WritePort(), RdWrPort(), IprPort() ]
diff --git a/src/cpu/o3/FuncUnitConfig.py b/src/cpu/o3/FuncUnitConfig.py
new file mode 100644
index 000000000..954381f86
--- /dev/null
+++ b/src/cpu/o3/FuncUnitConfig.py
@@ -0,0 +1,69 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Kevin Lim
+
+from m5.SimObject import SimObject
+from m5.params import *
+from FuncUnit import *
+
+class IntALU(FUDesc):
+    opList = [ OpDesc(opClass='IntAlu') ]
+    count = 6
+
+class IntMultDiv(FUDesc):
+    opList = [ OpDesc(opClass='IntMult', opLat=3),
+               OpDesc(opClass='IntDiv', opLat=20, issueLat=19) ]
+    count=2
+
+class FP_ALU(FUDesc):
+    opList = [ OpDesc(opClass='FloatAdd', opLat=2),
+               OpDesc(opClass='FloatCmp', opLat=2),
+               OpDesc(opClass='FloatCvt', opLat=2) ]
+    count = 4
+
+class FP_MultDiv(FUDesc):
+    opList = [ OpDesc(opClass='FloatMult', opLat=4),
+               OpDesc(opClass='FloatDiv', opLat=12, issueLat=12),
+               OpDesc(opClass='FloatSqrt', opLat=24, issueLat=24) ]
+    count = 2
+
+class ReadPort(FUDesc):
+    opList = [ OpDesc(opClass='MemRead') ]
+    count = 0
+
+class WritePort(FUDesc):
+    opList = [ OpDesc(opClass='MemWrite') ]
+    count = 0
+
+class RdWrPort(FUDesc):
+    opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite') ]
+    count = 4
+
+class IprPort(FUDesc):
+    opList = [ OpDesc(opClass='IprAccess', opLat = 3, issueLat = 3) ]
+    count = 1
+
diff --git a/src/python/m5/objects/O3CPU.py b/src/cpu/o3/O3CPU.py
index 5fba4e96f..e031faefa 100644
--- a/src/python/m5/objects/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -1,10 +1,40 @@
+# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Kevin Lim
+
 from m5.params import *
 from m5.proxy import *
 from m5 import build_env
 from BaseCPU import BaseCPU
-from Checker import O3Checker
 from FUPool import *
 
+if build_env['USE_CHECKER']:
+    from O3Checker import O3Checker
+
 class DerivO3CPU(BaseCPU):
     type = 'DerivO3CPU'
     activity = Param.Unsigned(0, "Initial count")
diff --git a/src/cpu/o3/O3Checker.py b/src/cpu/o3/O3Checker.py
new file mode 100644
index 000000000..43a71d67b
--- /dev/null
+++ b/src/cpu/o3/O3Checker.py
@@ -0,0 +1,43 @@
+# Copyright (c) 2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+from m5.params import *
+from m5 import build_env
+from BaseCPU import BaseCPU
+
+class O3Checker(BaseCPU):
+    type = 'O3Checker'
+    exitOnError = Param.Bool(False, "Exit on an error")
+    updateOnError = Param.Bool(False,
+        "Update the checker with the main CPU's state on an error")
+    warnOnlyOnLoadError = Param.Bool(False,
+        "If a load result is incorrect, only print a warning and do not exit")
+    function_trace = Param.Bool(False, "Enable function trace")
+    function_trace_start = Param.Tick(0, "Cycle to start function trace")
+    if build_env['FULL_SYSTEM']:
+        profile = Param.Latency('0ns', "trace the kernel stack")
diff --git a/src/cpu/o3/SConscript b/src/cpu/o3/SConscript
index bb1dfb613..ad61ad228 100755
--- a/src/cpu/o3/SConscript
+++ b/src/cpu/o3/SConscript
@@ -33,6 +33,10 @@ import sys
 Import('*')
 
 if 'O3CPU' in env['CPU_MODELS']:
+    SimObject('FUPool.py')
+    SimObject('FuncUnitConfig.py')
+    SimObject('O3CPU.py')
+
     Source('base_dyn_inst.cc')
     Source('bpred_unit.cc')
     Source('commit.cc')
@@ -71,6 +75,7 @@ if 'O3CPU' in env['CPU_MODELS']:
         sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA'])
 
     if env['USE_CHECKER']:
+        SimObject('O3Checker.py')
         Source('checker_builder.cc')
 
 if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']:
diff --git a/src/python/m5/objects/OzoneCPU.py b/src/cpu/ozone/OzoneCPU.py
index 0913e044c..b9cfb448f 100644
--- a/src/python/m5/objects/OzoneCPU.py
+++ b/src/cpu/ozone/OzoneCPU.py
@@ -1,13 +1,45 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Kevin Lim
+
 from m5.params import *
 from m5 import build_env
 from BaseCPU import BaseCPU
 
+if build_env['USE_CHECKER']:
+    from OzoneChecker import OzoneChecker
+
 class DerivOzoneCPU(BaseCPU):
     type = 'DerivOzoneCPU'
 
     numThreads = Param.Unsigned("number of HW thread contexts")
 
-    checker = Param.BaseCPU("Checker CPU")
+    if build_env['USE_CHECKER']:
+        checker = Param.BaseCPU("Checker CPU")
     if build_env['FULL_SYSTEM']:
         profile = Param.Latency('0ns', "trace the kernel stack")
 
diff --git a/src/cpu/ozone/OzoneChecker.py b/src/cpu/ozone/OzoneChecker.py
new file mode 100644
index 000000000..f20b8770e
--- /dev/null
+++ b/src/cpu/ozone/OzoneChecker.py
@@ -0,0 +1,43 @@
+# Copyright (c) 2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+from m5.params import *
+from m5 import build_env
+from BaseCPU import BaseCPU
+
+class OzoneChecker(BaseCPU):
+    type = 'OzoneChecker'
+    exitOnError = Param.Bool(False, "Exit on an error")
+    updateOnError = Param.Bool(False,
+        "Update the checker with the main CPU's state on an error")
+    warnOnlyOnLoadError = Param.Bool(False,
+        "If a load result is incorrect, only print a warning and do not exit")
+    function_trace = Param.Bool(False, "Enable function trace")
+    function_trace_start = Param.Tick(0, "Cycle to start function trace")
+    if build_env['FULL_SYSTEM']:
+        profile = Param.Latency('0ns', "trace the kernel stack")
diff --git a/src/cpu/ozone/SConscript b/src/cpu/ozone/SConscript
index 4a040684a..cb2006456 100644
--- a/src/cpu/ozone/SConscript
+++ b/src/cpu/ozone/SConscript
@@ -31,6 +31,9 @@
 Import('*')
 
 if 'OzoneCPU' in env['CPU_MODELS']:
+    SimObject('OzoneCPU.py')
+    SimObject('SimpleOzoneCPU.py')
+
     need_bp_unit = True
     Source('base_dyn_inst.cc')
     Source('bpred_unit.cc')
@@ -42,4 +45,5 @@ if 'OzoneCPU' in env['CPU_MODELS']:
     Source('lw_lsq.cc')
     Source('rename_table.cc')
     if env['USE_CHECKER']:
+        SimObject('OzoneChecker.py')
         Source('checker_builder.cc')
diff --git a/src/python/m5/objects/SimpleOzoneCPU.py b/src/cpu/ozone/SimpleOzoneCPU.py
index 193f31b0f..93603092b 100644
--- a/src/python/m5/objects/SimpleOzoneCPU.py
+++ b/src/cpu/ozone/SimpleOzoneCPU.py
@@ -1,3 +1,31 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Kevin Lim
+
 from m5.params import *
 from m5 import build_env
 from BaseCPU import BaseCPU
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index d78162243..d1214223b 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -53,7 +53,6 @@
 #include "arch/vtophys.hh"
 #include "base/callback.hh"
 #include "cpu/profile.hh"
-#include "mem/physical.hh"
 #include "sim/faults.hh"
 #include "sim/sim_events.hh"
 #include "sim/sim_exit.hh"
diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py
new file mode 100644
index 000000000..e97f059c1
--- /dev/null
+++ b/src/cpu/simple/AtomicSimpleCPU.py
@@ -0,0 +1,43 @@
+# Copyright (c) 2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+from m5.params import *
+from m5 import build_env
+from BaseCPU import BaseCPU
+
+class AtomicSimpleCPU(BaseCPU):
+    type = 'AtomicSimpleCPU'
+    width = Param.Int(1, "CPU width")
+    simulate_stalls = Param.Bool(False, "Simulate cache stall cycles")
+    function_trace = Param.Bool(False, "Enable function trace")
+    function_trace_start = Param.Tick(0, "Cycle to start function trace")
+    if build_env['FULL_SYSTEM']:
+        profile = Param.Latency('0ns', "trace the kernel stack")
+    icache_port = Port("Instruction Port")
+    dcache_port = Port("Data Port")
+    _mem_ports = ['icache_port', 'dcache_port']
diff --git a/src/cpu/simple/SConscript b/src/cpu/simple/SConscript
index 9a6a80473..ccccab2b5 100644
--- a/src/cpu/simple/SConscript
+++ b/src/cpu/simple/SConscript
@@ -33,10 +33,12 @@ Import('*')
 need_simple_base = False
 if 'AtomicSimpleCPU' in env['CPU_MODELS']:
     need_simple_base = True
+    SimObject('AtomicSimpleCPU.py')
     Source('atomic.cc')
 
 if 'TimingSimpleCPU' in env['CPU_MODELS']:
     need_simple_base = True
+    SimObject('TimingSimpleCPU.py')
     Source('timing.cc')
 
 if need_simple_base:
diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py
new file mode 100644
index 000000000..2fcde175c
--- /dev/null
+++ b/src/cpu/simple/TimingSimpleCPU.py
@@ -0,0 +1,41 @@
+# Copyright (c) 2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+from m5.params import *
+from m5 import build_env
+from BaseCPU import BaseCPU
+
+class TimingSimpleCPU(BaseCPU):
+    type = 'TimingSimpleCPU'
+    function_trace = Param.Bool(False, "Enable function trace")
+    function_trace_start = Param.Tick(0, "Cycle to start function trace")
+    if build_env['FULL_SYSTEM']:
+        profile = Param.Latency('0ns', "trace the kernel stack")
+    icache_port = Port("Instruction Port")
+    dcache_port = Port("Data Port")
+    _mem_ports = ['icache_port', 'dcache_port']
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index d2718c5f9..5e078c502 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -70,7 +70,7 @@ using namespace std;
 using namespace TheISA;
 
 BaseSimpleCPU::BaseSimpleCPU(Params *p)
-    : BaseCPU(p), thread(NULL), predecoder(NULL)
+    : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL)
 {
 #if FULL_SYSTEM
     thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
@@ -329,18 +329,20 @@ BaseSimpleCPU::checkForInterrupts()
 Fault
 BaseSimpleCPU::setupFetchRequest(Request *req)
 {
+    uint64_t threadPC = thread->readPC();
+
     // set up memory request for instruction fetch
 #if ISA_HAS_DELAY_SLOT
-    DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",thread->readPC(),
+    DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC,
             thread->readNextPC(),thread->readNextNPC());
 #else
-    DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",thread->readPC(),
+    DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",threadPC,
             thread->readNextPC());
 #endif
 
     const Addr PCMask = ~(sizeof(MachInst) - 1);
     Addr fetchPC = thread->readPC() + fetchOffset;
-    req->setVirt(0, fetchPC & PCMask, sizeof(MachInst), 0, thread->readPC());
+    req->setVirt(0, fetchPC & PCMask, sizeof(MachInst), 0, threadPC());
 
     Fault fault = thread->translateInstReq(req);
 
@@ -413,6 +415,7 @@ BaseSimpleCPU::preExecute()
             fetchMicroOp(thread->readMicroPC());
     }
 
+#if TRACING_ON
     //If we decoded an instruction this "tick", record information about it.
     if(curStaticInst)
     {
@@ -426,6 +429,7 @@ BaseSimpleCPU::preExecute()
         thread->setInst(inst);
 #endif // FULL_SYSTEM
     }
+#endif // TRACING_ON
 }
 
 void
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 824914ad0..95848ee2c 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -38,7 +38,6 @@
 #include "config/full_system.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/thread_state.hh"
-#include "mem/physical.hh"
 #include "mem/request.hh"
 #include "sim/byteswap.hh"
 #include "sim/eventq.hh"
diff --git a/src/dev/BadDevice.py b/src/dev/BadDevice.py
new file mode 100644
index 000000000..4fc592184
--- /dev/null
+++ b/src/dev/BadDevice.py
@@ -0,0 +1,34 @@
+# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+from m5.params import *
+from Device import BasicPioDevice
+
+class BadDevice(BasicPioDevice):
+    type = 'BadDevice'
+    devicename = Param.String("Name of device to error on")
diff --git a/src/python/m5/objects/Device.py b/src/dev/Device.py
index 90fbfb552..adf262f26 100644
--- a/src/python/m5/objects/Device.py
+++ b/src/dev/Device.py
@@ -1,3 +1,31 @@
+# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
 from m5.params import *
 from m5.proxy import *
 from MemObject import MemObject
diff --git a/src/dev/DiskImage.py b/src/dev/DiskImage.py
new file mode 100644
index 000000000..af2407458
--- /dev/null
+++ b/src/dev/DiskImage.py
@@ -0,0 +1,44 @@
+# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+from m5.SimObject import SimObject
+from m5.params import *
+class DiskImage(SimObject):
+    type = 'DiskImage'
+    abstract = True
+    image_file = Param.String("disk image file")
+    read_only = Param.Bool(False, "read only image")
+
+class RawDiskImage(DiskImage):
+    type = 'RawDiskImage'
+
+class CowDiskImage(DiskImage):
+    type = 'CowDiskImage'
+    child = Param.DiskImage(RawDiskImage(read_only=True),
+                            "child image")
+    table_size = Param.Int(65536, "initial table size")
diff --git a/src/python/m5/objects/Ethernet.py b/src/dev/Ethernet.py
index bfe30950c..e81862a96 100644
--- a/src/python/m5/objects/Ethernet.py
+++ b/src/dev/Ethernet.py
@@ -1,8 +1,34 @@
+# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
-from m5 import build_env
-from Device import DmaDevice
 from Pci import PciDevice, PciConfigData
 
 class EtherInt(SimObject):
@@ -36,46 +62,19 @@ class EtherDump(SimObject):
     file = Param.String("dump file")
     maxlen = Param.Int(96, "max portion of packet data to dump")
 
-if build_env['ALPHA_TLASER']:
-
-    class EtherDev(DmaDevice):
-        type = 'EtherDev'
-        hardware_address = Param.EthernetAddr(NextEthernetAddr,
-            "Ethernet Hardware Address")
-
-        dma_data_free = Param.Bool(False, "DMA of Data is free")
-        dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
-        dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
-        dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
-        dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
-        dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
-        dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
-
-        rx_filter = Param.Bool(True, "Enable Receive Filter")
-        rx_delay = Param.Latency('1us', "Receive Delay")
-        tx_delay = Param.Latency('1us', "Transmit Delay")
-
-        intr_delay = Param.Latency('0us', "Interrupt Delay")
-        payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
-        physmem = Param.PhysicalMemory(Parent.any, "Physical Memory")
-        tlaser = Param.Turbolaser(Parent.any, "Turbolaser")
-
-    class EtherDevInt(EtherInt):
-        type = 'EtherDevInt'
-        device = Param.EtherDev("Ethernet device of this interface")
-
-
 class IGbE(PciDevice):
     type = 'IGbE'
     hardware_address = Param.String("Ethernet Hardware Address")
-    use_flow_control = Param.Bool(False, "Should we use xon/xoff flow contorl (UNIMPLMENTD)")
+    use_flow_control = Param.Bool(False,
+        "Should we use xon/xoff flow contorl (UNIMPLEMENTD)")
     rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO")
     tx_fifo_size = Param.MemorySize('384kB', "Size of the tx FIFO")
-    rx_desc_cache_size = Param.Int(64, "Number of enteries in the rx descriptor cache")
-    tx_desc_cache_size = Param.Int(64, "Number of enteries in the rx descriptor cache")
+    rx_desc_cache_size = Param.Int(64,
+        "Number of enteries in the rx descriptor cache")
+    tx_desc_cache_size = Param.Int(64,
+        "Number of enteries in the rx descriptor cache")
     clock = Param.Clock('500MHz', "Clock speed of the device")
 
-
 class IGbEPciData(PciConfigData):
     VendorID = 0x8086
     DeviceID = 0x1075
diff --git a/src/dev/Ide.py b/src/dev/Ide.py
new file mode 100644
index 000000000..6bbaad00e
--- /dev/null
+++ b/src/dev/Ide.py
@@ -0,0 +1,68 @@
+# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+from m5.SimObject import SimObject
+from m5.params import *
+from Pci import PciDevice, PciConfigData
+
+class IdeID(Enum): vals = ['master', 'slave']
+
+class IdeControllerPciData(PciConfigData):
+    VendorID = 0x8086
+    DeviceID = 0x7111
+    Command = 0x0
+    Status = 0x280
+    Revision = 0x0
+    ClassCode = 0x01
+    SubClassCode = 0x01
+    ProgIF = 0x85
+    BAR0 = 0x00000001
+    BAR1 = 0x00000001
+    BAR2 = 0x00000001
+    BAR3 = 0x00000001
+    BAR4 = 0x00000001
+    BAR5 = 0x00000001
+    InterruptLine = 0x1f
+    InterruptPin = 0x01
+    BAR0Size = '8B'
+    BAR1Size = '4B'
+    BAR2Size = '8B'
+    BAR3Size = '4B'
+    BAR4Size = '16B'
+
+class IdeDisk(SimObject):
+    type = 'IdeDisk'
+    delay = Param.Latency('1us', "Fixed disk delay in microseconds")
+    driveID = Param.IdeID('master', "Drive ID")
+    image = Param.DiskImage("Disk image")
+
+class IdeController(PciDevice):
+    type = 'IdeController'
+    disks = VectorParam.IdeDisk("IDE disks attached to this controller")
+
+    configdata =IdeControllerPciData()
diff --git a/src/python/m5/objects/Pci.py b/src/dev/Pci.py
index 9d40adbfe..b2c013f41 100644
--- a/src/python/m5/objects/Pci.py
+++ b/src/dev/Pci.py
@@ -1,3 +1,31 @@
+# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
diff --git a/src/dev/Platform.py b/src/dev/Platform.py
new file mode 100644
index 000000000..cb414121b
--- /dev/null
+++ b/src/dev/Platform.py
@@ -0,0 +1,35 @@
+# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
+class Platform(SimObject):
+    type = 'Platform'
+    abstract = True
+    intrctrl = Param.IntrControl(Parent.any, "interrupt controller")
diff --git a/src/dev/SConscript b/src/dev/SConscript
index ea529b536..2e0d75650 100644
--- a/src/dev/SConscript
+++ b/src/dev/SConscript
@@ -32,6 +32,17 @@
 Import('*')
 
 if env['FULL_SYSTEM']:
+    SimObject('BadDevice.py')
+    SimObject('Device.py')
+    SimObject('DiskImage.py')
+    SimObject('Ethernet.py')
+    SimObject('Ide.py')
+    SimObject('Pci.py')
+    SimObject('Platform.py')
+    SimObject('SimConsole.py')
+    SimObject('SimpleDisk.py')
+    SimObject('Uart.py')
+
     Source('baddev.cc')
     Source('disk_image.cc')
     Source('etherbus.cc')
diff --git a/src/dev/SimConsole.py b/src/dev/SimConsole.py
new file mode 100644
index 000000000..bb8420527
--- /dev/null
+++ b/src/dev/SimConsole.py
@@ -0,0 +1,39 @@
+# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
+
+class SimConsole(SimObject):
+    type = 'SimConsole'
+    append_name = Param.Bool(True, "append name() to filename")
+    intr_control = Param.IntrControl(Parent.any, "interrupt controller")
+    port = Param.TcpPort(3456, "listen port")
+    number = Param.Int(0, "console number")
+    output = Param.String('console', "file to dump output to")
diff --git a/src/dev/SimpleDisk.py b/src/dev/SimpleDisk.py
new file mode 100644
index 000000000..1c9193035
--- /dev/null
+++ b/src/dev/SimpleDisk.py
@@ -0,0 +1,35 @@
+# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
+class SimpleDisk(SimObject):
+    type = 'SimpleDisk'
+    disk = Param.DiskImage("Disk Image")
+    system = Param.System(Parent.any, "Sysetm Pointer")
diff --git a/src/dev/Uart.py b/src/dev/Uart.py
new file mode 100644
index 000000000..e32517a4c
--- /dev/null
+++ b/src/dev/Uart.py
@@ -0,0 +1,45 @@
+# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+from m5.params import *
+from m5.proxy import *
+from m5 import build_env
+from Device import BasicPioDevice
+
+class Uart(BasicPioDevice):
+    type = 'Uart'
+    abstract = True
+    sim_console = Param.SimConsole(Parent.any, "The console")
+
+class Uart8250(Uart):
+    type = 'Uart8250'
+
+if build_env['ALPHA_TLASER']:
+    class Uart8530(Uart):
+        type = 'Uart8530'
+
diff --git a/src/dev/alpha/AlphaConsole.py b/src/dev/alpha/AlphaConsole.py
new file mode 100644
index 000000000..43c7ef954
--- /dev/null
+++ b/src/dev/alpha/AlphaConsole.py
@@ -0,0 +1,38 @@
+# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+from m5.params import *
+from m5.proxy import *
+from Device import BasicPioDevice
+
+class AlphaConsole(BasicPioDevice):
+    type = 'AlphaConsole'
+    cpu = Param.BaseCPU(Parent.cpu[0], "Processor")
+    disk = Param.SimpleDisk("Simple Disk")
+    sim_console = Param.SimConsole(Parent.any, "The Simulator Console")
+    system = Param.AlphaSystem(Parent.any, "system object")
diff --git a/src/dev/alpha/SConscript b/src/dev/alpha/SConscript
index c985fdd9f..8d7f5493b 100644
--- a/src/dev/alpha/SConscript
+++ b/src/dev/alpha/SConscript
@@ -32,6 +32,9 @@
 Import('*')
 
 if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'alpha':
+    SimObject('AlphaConsole.py')
+    SimObject('Tsunami.py')
+
     Source('console.cc')
     Source('tsunami.cc')
     Source('tsunami_cchip.cc')
diff --git a/src/python/m5/objects/Tsunami.py b/src/dev/alpha/Tsunami.py
index 85105ff20..484976c09 100644
--- a/src/python/m5/objects/Tsunami.py
+++ b/src/dev/alpha/Tsunami.py
@@ -1,3 +1,31 @@
+# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
 from m5.params import *
 from m5.proxy import *
 from Device import BasicPioDevice, IsaFake, BadAddr
diff --git a/src/dev/sparc/SConscript b/src/dev/sparc/SConscript
index 8511b16fb..2ebf9fe05 100644
--- a/src/dev/sparc/SConscript
+++ b/src/dev/sparc/SConscript
@@ -32,6 +32,8 @@
 Import('*')
 
 if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'sparc':
+    SimObject('T1000.py')
+
     Source('dtod.cc')
     Source('iob.cc')
     Source('t1000.cc')
diff --git a/src/python/m5/objects/T1000.py b/src/dev/sparc/T1000.py
index 0acfa0920..a033e27e2 100644
--- a/src/python/m5/objects/T1000.py
+++ b/src/dev/sparc/T1000.py
@@ -1,3 +1,31 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
 from m5.params import *
 from m5.proxy import *
 from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
diff --git a/src/mem/Bridge.py b/src/mem/Bridge.py
new file mode 100644
index 000000000..8377221cd
--- /dev/null
+++ b/src/mem/Bridge.py
@@ -0,0 +1,44 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ali Saidi
+
+from m5.params import *
+from MemObject import MemObject
+
+class Bridge(MemObject):
+    type = 'Bridge'
+    side_a = Port('Side A port')
+    side_b = Port('Side B port')
+    req_size_a = Param.Int(16, "The number of requests to buffer")
+    req_size_b = Param.Int(16, "The number of requests to buffer")
+    resp_size_a = Param.Int(16, "The number of requests to buffer")
+    resp_size_b = Param.Int(16, "The number of requests to buffer")
+    delay = Param.Latency('0ns', "The latency of this bridge")
+    nack_delay = Param.Latency('0ns', "The latency of this bridge")
+    write_ack = Param.Bool(False, "Should this bridge ack writes")
+    fix_partial_write_a = Param.Bool(False, "Should this bridge fixup partial block writes")
+    fix_partial_write_b = Param.Bool(False, "Should this bridge fixup partial block writes")
diff --git a/src/mem/Bus.py b/src/mem/Bus.py
new file mode 100644
index 000000000..247a1fe31
--- /dev/null
+++ b/src/mem/Bus.py
@@ -0,0 +1,49 @@
+# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+from m5 import build_env
+from m5.params import *
+from m5.proxy import *
+from MemObject import MemObject
+
+if build_env['FULL_SYSTEM']:
+    from Device import BadAddr
+
+class Bus(MemObject):
+    type = 'Bus'
+    port = VectorPort("vector port for connecting devices")
+    bus_id = Param.Int(0, "blah")
+    clock = Param.Clock("1GHz", "bus clock speed")
+    width = Param.Int(64, "bus width (bytes)")
+    responder_set = Param.Bool(False, "Did the user specify a default responder.")
+    block_size = Param.Int(64, "The default block size if one isn't set by a device attached to the bus.")
+    if build_env['FULL_SYSTEM']:
+        responder = BadAddr(pio_addr=0x0, pio_latency="1ps")
+        default = Port(Self.responder.pio, "Default port for requests that aren't handled by a device.")
+    else:
+        default = Port("Default port for requests that aren't handled by a device.")
diff --git a/src/mem/MemObject.py b/src/mem/MemObject.py
new file mode 100644
index 000000000..269cf4403
--- /dev/null
+++ b/src/mem/MemObject.py
@@ -0,0 +1,34 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+
+from m5.SimObject import SimObject
+from m5.SimObject import SimObject
+
+class MemObject(SimObject):
+    type = 'MemObject'
+    abstract = True
diff --git a/src/mem/PhysicalMemory.py b/src/mem/PhysicalMemory.py
new file mode 100644
index 000000000..2ef3df7c1
--- /dev/null
+++ b/src/mem/PhysicalMemory.py
@@ -0,0 +1,57 @@
+# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+from m5.params import *
+from m5.proxy import *
+from MemObject import *
+
+class PhysicalMemory(MemObject):
+    type = 'PhysicalMemory'
+    port = VectorPort("the access port")
+    range = Param.AddrRange(AddrRange('128MB'), "Device Address")
+    file = Param.String('', "memory mapped file")
+    latency = Param.Latency('1t', "latency of an access")
+    zero = Param.Bool(False, "zero initialize memory")
+
+class DRAMMemory(PhysicalMemory):
+    type = 'DRAMMemory'
+    # Many of these should be observed from the configuration
+    cpu_ratio = Param.Int(5,"ratio between CPU speed and memory bus speed")
+    mem_type = Param.String("SDRAM", "Type of DRAM (DRDRAM, SDRAM)")
+    mem_actpolicy = Param.String("open", "Open/Close policy")
+    memctrladdr_type = Param.String("interleaved", "Mapping interleaved or direct")
+    bus_width = Param.Int(16, "")
+    act_lat = Param.Int(2, "RAS to CAS delay")
+    cas_lat = Param.Int(1, "CAS delay")
+    war_lat = Param.Int(2, "write after read delay")
+    pre_lat = Param.Int(2, "precharge delay")
+    dpl_lat = Param.Int(2, "data in to precharge delay")
+    trc_lat = Param.Int(6, "row cycle delay")
+    num_banks = Param.Int(4, "Number of Banks")
+    num_cpus = Param.Int(4, "Number of CPUs connected to DRAM")
+
diff --git a/src/mem/SConscript b/src/mem/SConscript
index 61fb766d6..bbb1e96fe 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -30,6 +30,11 @@
 
 Import('*')
 
+SimObject('Bridge.py')
+SimObject('Bus.py')
+SimObject('PhysicalMemory.py')
+SimObject('MemObject.py')
+
 Source('bridge.cc')
 Source('bus.cc')
 Source('dram.cc')
diff --git a/src/python/m5/objects/BaseCache.py b/src/mem/cache/BaseCache.py
index 7df5215e4..4b98f6b30 100644
--- a/src/python/m5/objects/BaseCache.py
+++ b/src/mem/cache/BaseCache.py
@@ -1,3 +1,31 @@
+# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
 from m5.params import *
 from MemObject import MemObject
 
diff --git a/src/mem/cache/SConscript b/src/mem/cache/SConscript
index 7150719ad..546e037bd 100644
--- a/src/mem/cache/SConscript
+++ b/src/mem/cache/SConscript
@@ -30,6 +30,8 @@
 
 Import('*')
 
+SimObject('BaseCache.py')
+
 Source('base_cache.cc')
 Source('cache.cc')
 Source('cache_builder.cc')
diff --git a/src/python/m5/objects/CoherenceProtocol.py b/src/mem/cache/coherence/CoherenceProtocol.py
index 82adb6862..82adb6862 100644
--- a/src/python/m5/objects/CoherenceProtocol.py
+++ b/src/mem/cache/coherence/CoherenceProtocol.py
diff --git a/src/mem/cache/coherence/SConscript b/src/mem/cache/coherence/SConscript
index 03a2d85d7..4f5966140 100644
--- a/src/mem/cache/coherence/SConscript
+++ b/src/mem/cache/coherence/SConscript
@@ -30,6 +30,8 @@
 
 Import('*')
 
+SimObject('CoherenceProtocol.py')
+
 Source('coherence_protocol.cc')
 Source('uni_coherence.cc')
 
diff --git a/src/python/m5/objects/Repl.py b/src/mem/cache/tags/Repl.py
index b76aa1d6e..b76aa1d6e 100644
--- a/src/python/m5/objects/Repl.py
+++ b/src/mem/cache/tags/Repl.py
diff --git a/src/mem/cache/tags/SConscript b/src/mem/cache/tags/SConscript
index baf71f687..3fcaec4fa 100644
--- a/src/mem/cache/tags/SConscript
+++ b/src/mem/cache/tags/SConscript
@@ -38,5 +38,6 @@ Source('split.cc')
 Source('split_lifo.cc')
 Source('split_lru.cc')
 
+SimObject('Repl.py')
 Source('repl/gen.cc')
 Source('repl/repl.cc')
diff --git a/src/mem/packet.cc b/src/mem/packet.cc
index 2463a19ba..f70c0cec3 100644
--- a/src/mem/packet.cc
+++ b/src/mem/packet.cc
@@ -192,11 +192,12 @@ fixPacket(PacketPtr func, PacketPtr timing)
             func->flags |= SATISFIED;
             return false;
         } else {
-            // In this case the timing packet only partially satisfies the
-            // requset, so we would need more information to make this work.
-            // Like bytes valid in the packet or something, so the request could
-            // continue and get this bit of possibly newer data along with the
-            // older data not written to yet.
+            // In this case the timing packet only partially satisfies
+            // the request, so we would need more information to make
+            // this work.  Like bytes valid in the packet or
+            // something, so the request could continue and get this
+            // bit of possibly newer data along with the older data
+            // not written to yet.
             panic("Timing packet only partially satisfies the functional"
                     "request. Now what?");
         }
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index dc23e9f6d..c1e6a1e7f 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -506,16 +506,18 @@ class Packet
     bool intersect(PacketPtr p);
 };
 
-/** This function given a functional packet and a timing packet either satisfies
- * the timing packet, or updates the timing packet to reflect the updated state
- * in the timing packet. It returns if the functional packet should continue to
- * traverse the memory hierarchy or not.
+/** This function given a functional packet and a timing packet either
+ * satisfies the timing packet, or updates the timing packet to
+ * reflect the updated state in the timing packet. It returns if the
+ * functional packet should continue to traverse the memory hierarchy
+ * or not.
  */
 bool fixPacket(PacketPtr func, PacketPtr timing);
 
-/** This function is a wrapper for the fixPacket field that toggles the hasData bit
- * it is used when a response is waiting in the caches, but hasn't been marked as a
- * response yet (so the fixPacket needs to get the correct value for the hasData)
+/** This function is a wrapper for the fixPacket field that toggles
+ * the hasData bit it is used when a response is waiting in the
+ * caches, but hasn't been marked as a response yet (so the fixPacket
+ * needs to get the correct value for the hasData)
  */
 bool fixDelayedResponsePacket(PacketPtr func, PacketPtr timing);
 
diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index 6621c36cf..9d840fe69 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -414,20 +414,7 @@ PhysicalMemory::MemoryPort::recvAtomic(PacketPtr pkt)
 void
 PhysicalMemory::MemoryPort::recvFunctional(PacketPtr pkt)
 {
-    //Since we are overriding the function, make sure to have the impl of the
-    //check or functional accesses here.
-    std::list<std::pair<Tick,PacketPtr> >::iterator i = transmitList.begin();
-    std::list<std::pair<Tick,PacketPtr> >::iterator end = transmitList.end();
-    bool notDone = true;
-
-    while (i != end && notDone) {
-        PacketPtr target = i->second;
-        // If the target contains data, and it overlaps the
-        // probed request, need to update data
-        if (target->intersect(pkt))
-            notDone = fixPacket(pkt, target);
-        i++;
-    }
+    checkFunctional(pkt);
 
     // Default implementation of SimpleTimingPort::recvFunctional()
     // calls recvAtomic() and throws away the latency; we can save a
diff --git a/src/mem/tport.cc b/src/mem/tport.cc
index 9a4bd7967..ed4c0c172 100644
--- a/src/mem/tport.cc
+++ b/src/mem/tport.cc
@@ -31,23 +31,30 @@
 #include "mem/tport.hh"
 
 void
-SimpleTimingPort::recvFunctional(PacketPtr pkt)
+SimpleTimingPort::checkFunctional(PacketPtr pkt)
 {
-    std::list<std::pair<Tick,PacketPtr> >::iterator i = transmitList.begin();
-    std::list<std::pair<Tick,PacketPtr> >::iterator end = transmitList.end();
-    bool notDone = true;
+    DeferredPacketIterator i = transmitList.begin();
+    DeferredPacketIterator end = transmitList.end();
 
-    while (i != end && notDone) {
-        PacketPtr target = i->second;
+    for (; i != end; ++i) {
+        PacketPtr target = i->pkt;
         // If the target contains data, and it overlaps the
         // probed request, need to update data
-        if (target->intersect(pkt))
-            notDone = fixPacket(pkt, target);
-
-        i++;
+        if (target->intersect(pkt)) {
+            if (!fixPacket(pkt, target)) {
+                // fixPacket returns true for continue, false for done
+                return;
+            }
+        }
     }
+}
 
-    //Then just do an atomic access and throw away the returned latency
+void
+SimpleTimingPort::recvFunctional(PacketPtr pkt)
+{
+    checkFunctional(pkt);
+
+    // Just do an atomic access and throw away the returned latency
     if (pkt->result != Packet::Success)
         recvAtomic(pkt);
 }
@@ -65,93 +72,94 @@ SimpleTimingPort::recvTiming(PacketPtr pkt)
     // turn packet around to go back to requester if response expected
     if (pkt->needsResponse()) {
         pkt->makeTimingResponse();
-        sendTiming(pkt, latency);
+        schedSendTiming(pkt, curTick + latency);
     }
-    else {
-        if (pkt->cmd != MemCmd::UpgradeReq)
-        {
-            delete pkt->req;
-            delete pkt;
-        }
+    else if (pkt->cmd != MemCmd::UpgradeReq) {
+        delete pkt->req;
+        delete pkt;
     }
     return true;
 }
 
-void
-SimpleTimingPort::recvRetry()
-{
-    assert(!transmitList.empty());
-    if (Port::sendTiming(transmitList.front().second)) {
-        transmitList.pop_front();
-        DPRINTF(Bus, "No Longer waiting on retry\n");
-        if (!transmitList.empty()) {
-            Tick time = transmitList.front().first;
-            sendEvent.schedule(time <= curTick ? curTick+1 : time);
-        }
-    }
-
-    if (transmitList.empty() && drainEvent) {
-        drainEvent->process();
-        drainEvent = NULL;
-    }
-}
 
 void
-SimpleTimingPort::sendTiming(PacketPtr pkt, Tick time)
+SimpleTimingPort::schedSendTiming(PacketPtr pkt, Tick when)
 {
+    assert(when > curTick);
+
     // Nothing is on the list: add it and schedule an event
     if (transmitList.empty()) {
-        assert(!sendEvent.scheduled());
-        sendEvent.schedule(curTick+time);
-        transmitList.push_back(std::pair<Tick,PacketPtr>(time+curTick,pkt));
+        assert(!sendEvent->scheduled());
+        sendEvent->schedule(when);
+        transmitList.push_back(DeferredPacket(when, pkt));
         return;
     }
 
     // something is on the list and this belongs at the end
-    if (time+curTick >= transmitList.back().first) {
-        transmitList.push_back(std::pair<Tick,PacketPtr>(time+curTick,pkt));
+    if (when >= transmitList.back().tick) {
+        transmitList.push_back(DeferredPacket(when, pkt));
         return;
     }
     // Something is on the list and this belongs somewhere else
-    std::list<std::pair<Tick,PacketPtr> >::iterator i = transmitList.begin();
-    std::list<std::pair<Tick,PacketPtr> >::iterator end = transmitList.end();
-    bool done = false;
+    DeferredPacketIterator i = transmitList.begin();
+    DeferredPacketIterator end = transmitList.end();
 
-    while (i != end && !done) {
-        if (time+curTick < i->first) {
+    for (; i != end; ++i) {
+        if (when < i->tick) {
             if (i == transmitList.begin()) {
                 //Inserting at begining, reschedule
-                sendEvent.reschedule(time+curTick);
+                sendEvent->reschedule(when);
             }
-            transmitList.insert(i,std::pair<Tick,PacketPtr>(time+curTick,pkt));
-            done = true;
+            transmitList.insert(i, DeferredPacket(when, pkt));
+            return;
         }
-        i++;
     }
-    assert(done);
+    assert(false); // should never get here
 }
 
+
 void
-SimpleTimingPort::SendEvent::process()
+SimpleTimingPort::sendDeferredPacket()
 {
-    assert(port->transmitList.size());
-    assert(port->transmitList.front().first <= curTick);
-    if (port->Port::sendTiming(port->transmitList.front().second)) {
+    assert(deferredPacketReady());
+    bool success = sendTiming(transmitList.front().pkt);
+
+    if (success) {
         //send successful, remove packet
-        port->transmitList.pop_front();
-        if (!port->transmitList.empty()) {
-            Tick time = port->transmitList.front().first;
-            schedule(time <= curTick ? curTick+1 : time);
+        transmitList.pop_front();
+        if (!transmitList.empty()) {
+            Tick time = transmitList.front().tick;
+            sendEvent->schedule(time <= curTick ? curTick+1 : time);
         }
-        if (port->transmitList.empty() && port->drainEvent) {
-            port->drainEvent->process();
-            port->drainEvent = NULL;
+
+        if (transmitList.empty() && drainEvent) {
+            drainEvent->process();
+            drainEvent = NULL;
         }
-        return;
     }
-    // send unsuccessful (due to flow control).  Will get retry
-    // callback later; save for then if not already
-    DPRINTF(Bus, "Waiting on retry\n");
+
+    waitingOnRetry = !success;
+
+    if (waitingOnRetry) {
+        DPRINTF(Bus, "Send failed, waiting on retry\n");
+    }
+}
+
+
+void
+SimpleTimingPort::recvRetry()
+{
+    DPRINTF(Bus, "Received retry\n");
+    assert(waitingOnRetry);
+    sendDeferredPacket();
+}
+
+
+void
+SimpleTimingPort::processSendEvent()
+{
+    assert(!waitingOnRetry);
+    sendDeferredPacket();
 }
 
 
diff --git a/src/mem/tport.hh b/src/mem/tport.hh
index 3d28ea3e5..ea0f05ed1 100644
--- a/src/mem/tport.hh
+++ b/src/mem/tport.hh
@@ -58,9 +58,26 @@
 class SimpleTimingPort : public Port
 {
   protected:
+    /** A deferred packet, buffered to transmit later. */
+    class DeferredPacket {
+      public:
+        Tick tick;      ///< The tick when the packet is ready to transmit
+        PacketPtr pkt;  ///< Pointer to the packet to transmit
+        DeferredPacket(Tick t, PacketPtr p)
+            : tick(t), pkt(p)
+        {}
+    };
+
+    typedef std::list<DeferredPacket> DeferredPacketList;
+    typedef std::list<DeferredPacket>::iterator DeferredPacketIterator;
+
     /** A list of outgoing timing response packets that haven't been
      * serviced yet. */
-    std::list<std::pair<Tick,PacketPtr> > transmitList;
+    DeferredPacketList transmitList;
+
+    /** This function attempts to send deferred packets.  Scheduled to
+     * be called in the future via SendEvent. */
+    void processSendEvent();
 
     /**
      * This class is used to implemented sendTiming() with a delay. When
@@ -68,32 +85,38 @@ class SimpleTimingPort : public Port
      * When the event time expires it attempts to send the packet.
      * If it cannot, the packet sent when recvRetry() is called.
      **/
-    class SendEvent : public Event
-    {
-        SimpleTimingPort *port;
-
-      public:
-        SendEvent(SimpleTimingPort *p)
-            : Event(&mainEventQueue), port(p)
-        { }
-
-        virtual void process();
+    typedef EventWrapper<SimpleTimingPort, &SimpleTimingPort::processSendEvent>
+            SendEvent;
 
-        virtual const char *description()
-        { return "Future scheduled sendTiming event"; }
-    };
-
-    SendEvent sendEvent;
+    Event *sendEvent;
 
     /** If we need to drain, keep the drain event around until we're done
      * here.*/
     Event *drainEvent;
 
+    /** Remember whether we're awaiting a retry from the bus. */
+    bool waitingOnRetry;
+
+    /** Check the list of buffered packets against the supplied
+     * functional request. */
+    void checkFunctional(PacketPtr funcPkt);
+
+    /** Check whether we have a packet ready to go on the transmit list. */
+    bool deferredPacketReady()
+    { return !transmitList.empty() && transmitList.front().tick <= curTick; }
+
     /** Schedule a sendTiming() event to be called in the future.
      * @param pkt packet to send
-     * @param time increment from now (in ticks) to send packet
+     * @param absolute time (in ticks) to send packet
+     */
+    void schedSendTiming(PacketPtr pkt, Tick when);
+
+    /** Attempt to send the packet at the head of the deferred packet
+     * list.  Caller must guarantee that the deferred packet list is
+     * non-empty and that the head packet is scheduled for curTick (or
+     * earlier).
      */
-    void sendTiming(PacketPtr pkt, Tick time);
+    void sendDeferredPacket();
 
     /** This function is notification that the device should attempt to send a
      * packet again. */
@@ -115,9 +138,14 @@ class SimpleTimingPort : public Port
   public:
 
     SimpleTimingPort(std::string pname, MemObject *_owner = NULL)
-        : Port(pname, _owner), sendEvent(this), drainEvent(NULL)
+        : Port(pname, _owner),
+          sendEvent(new SendEvent(this)),
+          drainEvent(NULL),
+          waitingOnRetry(false)
     {}
 
+    ~SimpleTimingPort() { delete sendEvent; }
+
     /** Hook for draining timing accesses from the system.  The
      * associated SimObject's drain() functions should be implemented
      * something like this when this class is used:
diff --git a/src/python/SConscript b/src/python/SConscript
index 562278aa0..66b852d25 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -60,54 +60,3 @@ SwigSource('m5.internal', 'swig/sim_object.i')
 SwigSource('m5.internal', 'swig/stats.i')
 SwigSource('m5.internal', 'swig/trace.i')
 PySource('m5.internal', 'm5/internal/__init__.py')
-
-SimObject('m5/objects/AlphaConsole.py')
-SimObject('m5/objects/AlphaTLB.py')
-SimObject('m5/objects/BadDevice.py')
-SimObject('m5/objects/BaseCPU.py')
-SimObject('m5/objects/BaseCache.py')
-SimObject('m5/objects/BaseHier.py')
-SimObject('m5/objects/BaseMem.py')
-SimObject('m5/objects/BaseMemory.py')
-SimObject('m5/objects/BranchPred.py')
-SimObject('m5/objects/Bridge.py')
-SimObject('m5/objects/Bus.py')
-SimObject('m5/objects/Checker.py')
-SimObject('m5/objects/CoherenceProtocol.py')
-SimObject('m5/objects/DRAMMemory.py')
-SimObject('m5/objects/Device.py')
-SimObject('m5/objects/DiskImage.py')
-SimObject('m5/objects/Ethernet.py')
-SimObject('m5/objects/FUPool.py')
-SimObject('m5/objects/FastCPU.py')
-#SimObject('m5/objects/FreebsdSystem.py')
-SimObject('m5/objects/FuncUnit.py')
-SimObject('m5/objects/FuncUnitConfig.py')
-SimObject('m5/objects/FunctionalMemory.py')
-SimObject('m5/objects/HierParams.py')
-SimObject('m5/objects/Ide.py')
-SimObject('m5/objects/IntrControl.py')
-SimObject('m5/objects/LinuxSystem.py')
-SimObject('m5/objects/MainMemory.py')
-SimObject('m5/objects/MemObject.py')
-SimObject('m5/objects/MemTest.py')
-SimObject('m5/objects/MemoryController.py')
-SimObject('m5/objects/O3CPU.py')
-SimObject('m5/objects/OzoneCPU.py')
-SimObject('m5/objects/Pci.py')
-SimObject('m5/objects/PhysicalMemory.py')
-SimObject('m5/objects/Platform.py')
-SimObject('m5/objects/Process.py')
-SimObject('m5/objects/Repl.py')
-SimObject('m5/objects/Root.py')
-SimObject('m5/objects/Sampler.py')
-SimObject('m5/objects/SimConsole.py')
-SimObject('m5/objects/SimpleCPU.py')
-SimObject('m5/objects/SimpleDisk.py')
-#SimObject('m5/objects/SimpleOzoneCPU.py')
-SimObject('m5/objects/SparcTLB.py')
-SimObject('m5/objects/System.py')
-SimObject('m5/objects/T1000.py')
-#SimObject('m5/objects/Tru64System.py')
-SimObject('m5/objects/Tsunami.py')
-SimObject('m5/objects/Uart.py')
diff --git a/src/python/m5/objects/AlphaConsole.py b/src/python/m5/objects/AlphaConsole.py
deleted file mode 100644
index f968aaa40..000000000
--- a/src/python/m5/objects/AlphaConsole.py
+++ /dev/null
@@ -1,10 +0,0 @@
-from m5.params import *
-from m5.proxy import *
-from Device import BasicPioDevice
-
-class AlphaConsole(BasicPioDevice):
-    type = 'AlphaConsole'
-    cpu = Param.BaseCPU(Parent.cpu[0], "Processor")
-    disk = Param.SimpleDisk("Simple Disk")
-    sim_console = Param.SimConsole(Parent.any, "The Simulator Console")
-    system = Param.AlphaSystem(Parent.any, "system object")
diff --git a/src/python/m5/objects/AlphaTLB.py b/src/python/m5/objects/AlphaTLB.py
deleted file mode 100644
index af7c04a84..000000000
--- a/src/python/m5/objects/AlphaTLB.py
+++ /dev/null
@@ -1,14 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-class AlphaTLB(SimObject):
-    type = 'AlphaTLB'
-    abstract = True
-    size = Param.Int("TLB size")
-
-class AlphaDTB(AlphaTLB):
-    type = 'AlphaDTB'
-    size = 64
-
-class AlphaITB(AlphaTLB):
-    type = 'AlphaITB'
-    size = 48
diff --git a/src/python/m5/objects/BadDevice.py b/src/python/m5/objects/BadDevice.py
deleted file mode 100644
index 919623887..000000000
--- a/src/python/m5/objects/BadDevice.py
+++ /dev/null
@@ -1,6 +0,0 @@
-from m5.params import *
-from Device import BasicPioDevice
-
-class BadDevice(BasicPioDevice):
-    type = 'BadDevice'
-    devicename = Param.String("Name of device to error on")
diff --git a/src/python/m5/objects/Bridge.py b/src/python/m5/objects/Bridge.py
deleted file mode 100644
index 33b24ad3c..000000000
--- a/src/python/m5/objects/Bridge.py
+++ /dev/null
@@ -1,16 +0,0 @@
-from m5.params import *
-from MemObject import MemObject
-
-class Bridge(MemObject):
-    type = 'Bridge'
-    side_a = Port('Side A port')
-    side_b = Port('Side B port')
-    req_size_a = Param.Int(16, "The number of requests to buffer")
-    req_size_b = Param.Int(16, "The number of requests to buffer")
-    resp_size_a = Param.Int(16, "The number of requests to buffer")
-    resp_size_b = Param.Int(16, "The number of requests to buffer")
-    delay = Param.Latency('0ns', "The latency of this bridge")
-    nack_delay = Param.Latency('0ns', "The latency of this bridge")
-    write_ack = Param.Bool(False, "Should this bridge ack writes")
-    fix_partial_write_a = Param.Bool(False, "Should this bridge fixup partial block writes")
-    fix_partial_write_b = Param.Bool(False, "Should this bridge fixup partial block writes")
diff --git a/src/python/m5/objects/Bus.py b/src/python/m5/objects/Bus.py
deleted file mode 100644
index 48dbbe307..000000000
--- a/src/python/m5/objects/Bus.py
+++ /dev/null
@@ -1,19 +0,0 @@
-from m5 import build_env
-from m5.params import *
-from m5.proxy import *
-from MemObject import MemObject
-from Device import BadAddr
-
-class Bus(MemObject):
-    type = 'Bus'
-    port = VectorPort("vector port for connecting devices")
-    bus_id = Param.Int(0, "blah")
-    clock = Param.Clock("1GHz", "bus clock speed")
-    width = Param.Int(64, "bus width (bytes)")
-    responder_set = Param.Bool(False, "Did the user specify a default responder.")
-    block_size = Param.Int(64, "The default block size if one isn't set by a device attached to the bus.")
-    if build_env['FULL_SYSTEM']:
-        responder = BadAddr(pio_addr=0x0, pio_latency="1ps")
-        default = Port(Self.responder.pio, "Default port for requests that aren't handled by a device.")
-    else:
-        default = Port("Default port for requests that aren't handled by a device.")
diff --git a/src/python/m5/objects/DiskImage.py b/src/python/m5/objects/DiskImage.py
deleted file mode 100644
index d0ada7ee1..000000000
--- a/src/python/m5/objects/DiskImage.py
+++ /dev/null
@@ -1,16 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-class DiskImage(SimObject):
-    type = 'DiskImage'
-    abstract = True
-    image_file = Param.String("disk image file")
-    read_only = Param.Bool(False, "read only image")
-
-class RawDiskImage(DiskImage):
-    type = 'RawDiskImage'
-
-class CowDiskImage(DiskImage):
-    type = 'CowDiskImage'
-    child = Param.DiskImage(RawDiskImage(read_only=True),
-                            "child image")
-    table_size = Param.Int(65536, "initial table size")
diff --git a/src/python/m5/objects/FUPool.py b/src/python/m5/objects/FUPool.py
deleted file mode 100644
index 916183bd7..000000000
--- a/src/python/m5/objects/FUPool.py
+++ /dev/null
@@ -1,12 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-from FuncUnit import *
-from FuncUnitConfig import *
-
-class FUPool(SimObject):
-    type = 'FUPool'
-    FUList = VectorParam.FUDesc("list of FU's for this pool")
-
-class DefaultFUPool(FUPool):
-    FUList = [ IntALU(), IntMultDiv(), FP_ALU(), FP_MultDiv(), ReadPort(),
-               WritePort(), RdWrPort(), IprPort() ]
diff --git a/src/python/m5/objects/FuncUnit.py b/src/python/m5/objects/FuncUnit.py
deleted file mode 100644
index f0ad55f7a..000000000
--- a/src/python/m5/objects/FuncUnit.py
+++ /dev/null
@@ -1,18 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-
-class OpType(Enum):
-    vals = ['(null)', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd',
-            'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatDiv', 'FloatSqrt',
-            'MemRead', 'MemWrite', 'IprAccess', 'InstPrefetch']
-
-class OpDesc(SimObject):
-    type = 'OpDesc'
-    issueLat = Param.Int(1, "cycles until another can be issued")
-    opClass = Param.OpType("type of operation")
-    opLat = Param.Int(1, "cycles until result is available")
-
-class FUDesc(SimObject):
-    type = 'FUDesc'
-    count = Param.Int("number of these FU's available")
-    opList = VectorParam.OpDesc("operation classes for this FU type")
diff --git a/src/python/m5/objects/FuncUnitConfig.py b/src/python/m5/objects/FuncUnitConfig.py
deleted file mode 100644
index 43d7a4bb7..000000000
--- a/src/python/m5/objects/FuncUnitConfig.py
+++ /dev/null
@@ -1,41 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-from FuncUnit import *
-
-class IntALU(FUDesc):
-    opList = [ OpDesc(opClass='IntAlu') ]
-    count = 6
-
-class IntMultDiv(FUDesc):
-    opList = [ OpDesc(opClass='IntMult', opLat=3),
-               OpDesc(opClass='IntDiv', opLat=20, issueLat=19) ]
-    count=2
-
-class FP_ALU(FUDesc):
-    opList = [ OpDesc(opClass='FloatAdd', opLat=2),
-               OpDesc(opClass='FloatCmp', opLat=2),
-               OpDesc(opClass='FloatCvt', opLat=2) ]
-    count = 4
-
-class FP_MultDiv(FUDesc):
-    opList = [ OpDesc(opClass='FloatMult', opLat=4),
-               OpDesc(opClass='FloatDiv', opLat=12, issueLat=12),
-               OpDesc(opClass='FloatSqrt', opLat=24, issueLat=24) ]
-    count = 2
-
-class ReadPort(FUDesc):
-    opList = [ OpDesc(opClass='MemRead') ]
-    count = 0
-
-class WritePort(FUDesc):
-    opList = [ OpDesc(opClass='MemWrite') ]
-    count = 0
-
-class RdWrPort(FUDesc):
-    opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite') ]
-    count = 4
-
-class IprPort(FUDesc):
-    opList = [ OpDesc(opClass='IprAccess', opLat = 3, issueLat = 3) ]
-    count = 1
-
diff --git a/src/python/m5/objects/Ide.py b/src/python/m5/objects/Ide.py
deleted file mode 100644
index ef7e28785..000000000
--- a/src/python/m5/objects/Ide.py
+++ /dev/null
@@ -1,40 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-from Pci import PciDevice, PciConfigData
-
-class IdeID(Enum): vals = ['master', 'slave']
-
-class IdeControllerPciData(PciConfigData):
-    VendorID = 0x8086
-    DeviceID = 0x7111
-    Command = 0x0
-    Status = 0x280
-    Revision = 0x0
-    ClassCode = 0x01
-    SubClassCode = 0x01
-    ProgIF = 0x85
-    BAR0 = 0x00000001
-    BAR1 = 0x00000001
-    BAR2 = 0x00000001
-    BAR3 = 0x00000001
-    BAR4 = 0x00000001
-    BAR5 = 0x00000001
-    InterruptLine = 0x1f
-    InterruptPin = 0x01
-    BAR0Size = '8B'
-    BAR1Size = '4B'
-    BAR2Size = '8B'
-    BAR3Size = '4B'
-    BAR4Size = '16B'
-
-class IdeDisk(SimObject):
-    type = 'IdeDisk'
-    delay = Param.Latency('1us', "Fixed disk delay in microseconds")
-    driveID = Param.IdeID('master', "Drive ID")
-    image = Param.DiskImage("Disk image")
-
-class IdeController(PciDevice):
-    type = 'IdeController'
-    disks = VectorParam.IdeDisk("IDE disks attached to this controller")
-
-    configdata =IdeControllerPciData()
diff --git a/src/python/m5/objects/IntrControl.py b/src/python/m5/objects/IntrControl.py
deleted file mode 100644
index 398ba47f9..000000000
--- a/src/python/m5/objects/IntrControl.py
+++ /dev/null
@@ -1,6 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-from m5.proxy import *
-class IntrControl(SimObject):
-    type = 'IntrControl'
-    sys = Param.System(Parent.any, "the system we are part of")
diff --git a/src/python/m5/objects/MemObject.py b/src/python/m5/objects/MemObject.py
deleted file mode 100644
index 8982d553d..000000000
--- a/src/python/m5/objects/MemObject.py
+++ /dev/null
@@ -1,6 +0,0 @@
-from m5.SimObject import SimObject
-from m5.SimObject import SimObject
-
-class MemObject(SimObject):
-    type = 'MemObject'
-    abstract = True
diff --git a/src/python/m5/objects/MemTest.py b/src/python/m5/objects/MemTest.py
deleted file mode 100644
index 1219ddd4d..000000000
--- a/src/python/m5/objects/MemTest.py
+++ /dev/null
@@ -1,24 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-from m5.proxy import *
-from m5 import build_env
-
-class MemTest(SimObject):
-    type = 'MemTest'
-    max_loads = Param.Counter("number of loads to execute")
-    atomic = Param.Bool(False, "Execute tester in atomic mode? (or timing)\n")
-    memory_size = Param.Int(65536, "memory size")
-    percent_dest_unaligned = Param.Percent(50,
-        "percent of copy dest address that are unaligned")
-    percent_reads = Param.Percent(65, "target read percentage")
-    percent_source_unaligned = Param.Percent(50,
-        "percent of copy source address that are unaligned")
-    percent_functional = Param.Percent(50, "percent of access that are functional")
-    percent_uncacheable = Param.Percent(10,
-        "target uncacheable percentage")
-    progress_interval = Param.Counter(1000000,
-        "progress report interval (in accesses)")
-    trace_addr = Param.Addr(0, "address to trace")
-
-    test = Port("Port to the memory system to test")
-    functional = Port("Port to the functional memory used for verification")
diff --git a/src/python/m5/objects/PhysicalMemory.py b/src/python/m5/objects/PhysicalMemory.py
deleted file mode 100644
index 83dbc7710..000000000
--- a/src/python/m5/objects/PhysicalMemory.py
+++ /dev/null
@@ -1,29 +0,0 @@
-from m5.params import *
-from m5.proxy import *
-from MemObject import *
-
-class PhysicalMemory(MemObject):
-    type = 'PhysicalMemory'
-    port = VectorPort("the access port")
-    range = Param.AddrRange(AddrRange('128MB'), "Device Address")
-    file = Param.String('', "memory mapped file")
-    latency = Param.Latency('1t', "latency of an access")
-    zero = Param.Bool(False, "zero initialize memory")
-
-class DRAMMemory(PhysicalMemory):
-    type = 'DRAMMemory'
-    # Many of these should be observed from the configuration
-    cpu_ratio = Param.Int(5,"ratio between CPU speed and memory bus speed")
-    mem_type = Param.String("SDRAM", "Type of DRAM (DRDRAM, SDRAM)")
-    mem_actpolicy = Param.String("open", "Open/Close policy")
-    memctrladdr_type = Param.String("interleaved", "Mapping interleaved or direct")
-    bus_width = Param.Int(16, "")
-    act_lat = Param.Int(2, "RAS to CAS delay")
-    cas_lat = Param.Int(1, "CAS delay")
-    war_lat = Param.Int(2, "write after read delay")
-    pre_lat = Param.Int(2, "precharge delay")
-    dpl_lat = Param.Int(2, "data in to precharge delay")
-    trc_lat = Param.Int(6, "row cycle delay")
-    num_banks = Param.Int(4, "Number of Banks")
-    num_cpus = Param.Int(4, "Number of CPUs connected to DRAM")
-
diff --git a/src/python/m5/objects/Platform.py b/src/python/m5/objects/Platform.py
deleted file mode 100644
index ab2083eea..000000000
--- a/src/python/m5/objects/Platform.py
+++ /dev/null
@@ -1,7 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-from m5.proxy import *
-class Platform(SimObject):
-    type = 'Platform'
-    abstract = True
-    intrctrl = Param.IntrControl(Parent.any, "interrupt controller")
diff --git a/src/python/m5/objects/Process.py b/src/python/m5/objects/Process.py
deleted file mode 100644
index 79268e6f4..000000000
--- a/src/python/m5/objects/Process.py
+++ /dev/null
@@ -1,36 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-from m5.proxy import *
-class Process(SimObject):
-    type = 'Process'
-    abstract = True
-    output = Param.String('cout', 'filename for stdout/stderr')
-    system = Param.System(Parent.any, "system process will run on")
-
-class LiveProcess(Process):
-    type = 'LiveProcess'
-    executable = Param.String('', "executable (overrides cmd[0] if set)")
-    cmd = VectorParam.String("command line (executable plus arguments)")
-    env = VectorParam.String('', "environment settings")
-    cwd = Param.String('', "current working directory")
-    input = Param.String('cin', "filename for stdin")
-    uid = Param.Int(100, 'user id')
-    euid = Param.Int(100, 'effective user id')
-    gid = Param.Int(100, 'group id')
-    egid = Param.Int(100, 'effective group id')
-    pid = Param.Int(100, 'process id')
-    ppid = Param.Int(99, 'parent process id')
-
-class AlphaLiveProcess(LiveProcess):
-    type = 'AlphaLiveProcess'
-
-class SparcLiveProcess(LiveProcess):
-    type = 'SparcLiveProcess'
-
-class MipsLiveProcess(LiveProcess):
-    type = 'MipsLiveProcess'
-
-class EioProcess(Process):
-    type = 'EioProcess'
-    chkpt = Param.String('', "EIO checkpoint file name (optional)")
-    file = Param.String("EIO trace file name")
diff --git a/src/python/m5/objects/Root.py b/src/python/m5/objects/Root.py
deleted file mode 100644
index 2b0e736e7..000000000
--- a/src/python/m5/objects/Root.py
+++ /dev/null
@@ -1,6 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-
-class Root(SimObject):
-    type = 'Root'
-    dummy = Param.Int(0, "We don't support objects without params")
diff --git a/src/python/m5/objects/SimConsole.py b/src/python/m5/objects/SimConsole.py
deleted file mode 100644
index dfad18eb6..000000000
--- a/src/python/m5/objects/SimConsole.py
+++ /dev/null
@@ -1,11 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-from m5.proxy import *
-
-class SimConsole(SimObject):
-    type = 'SimConsole'
-    append_name = Param.Bool(True, "append name() to filename")
-    intr_control = Param.IntrControl(Parent.any, "interrupt controller")
-    port = Param.TcpPort(3456, "listen port")
-    number = Param.Int(0, "console number")
-    output = Param.String('console', "file to dump output to")
diff --git a/src/python/m5/objects/SimpleDisk.py b/src/python/m5/objects/SimpleDisk.py
deleted file mode 100644
index 099a77dbb..000000000
--- a/src/python/m5/objects/SimpleDisk.py
+++ /dev/null
@@ -1,7 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-from m5.proxy import *
-class SimpleDisk(SimObject):
-    type = 'SimpleDisk'
-    disk = Param.DiskImage("Disk Image")
-    system = Param.System(Parent.any, "Sysetm Pointer")
diff --git a/src/python/m5/objects/SparcTLB.py b/src/python/m5/objects/SparcTLB.py
deleted file mode 100644
index 06d2a8231..000000000
--- a/src/python/m5/objects/SparcTLB.py
+++ /dev/null
@@ -1,14 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-class SparcTLB(SimObject):
-    type = 'SparcTLB'
-    abstract = True
-    size = Param.Int("TLB size")
-
-class SparcDTB(SparcTLB):
-    type = 'SparcDTB'
-    size = 64
-
-class SparcITB(SparcTLB):
-    type = 'SparcITB'
-    size = 64
diff --git a/src/python/m5/objects/System.py b/src/python/m5/objects/System.py
deleted file mode 100644
index 810a320be..000000000
--- a/src/python/m5/objects/System.py
+++ /dev/null
@@ -1,68 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-from m5.proxy import *
-from m5 import build_env
-from PhysicalMemory import *
-
-class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing']
-
-class System(SimObject):
-    type = 'System'
-    physmem = Param.PhysicalMemory(Parent.any, "phsyical memory")
-    mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in")
-    if build_env['FULL_SYSTEM']:
-        boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
-                                             "boot processor frequency")
-        init_param = Param.UInt64(0, "numerical value to pass into simulator")
-        boot_osflags = Param.String("a", "boot flags to pass to the kernel")
-        kernel = Param.String("", "file that contains the kernel code")
-        readfile = Param.String("", "file to read startup script from")
-        symbolfile = Param.String("", "file to get the symbols from")
-
-class AlphaSystem(System):
-    type = 'AlphaSystem'
-    console = Param.String("file that contains the console code")
-    pal = Param.String("file that contains palcode")
-    system_type = Param.UInt64("Type of system we are emulating")
-    system_rev = Param.UInt64("Revision of system we are emulating")
-
-class SparcSystem(System):
-    type = 'SparcSystem'
-    _rom_base = 0xfff0000000
-    _nvram_base = 0x1f11000000
-    _hypervisor_desc_base = 0x1f12080000
-    _partition_desc_base = 0x1f12000000
-    # ROM for OBP/Reset/Hypervisor
-    rom = Param.PhysicalMemory(PhysicalMemory(range = AddrRange(_rom_base, size = '8MB')),
-            "Memory to hold the ROM data")
-    # nvram
-    nvram = Param.PhysicalMemory(
-            PhysicalMemory(range = AddrRange(_nvram_base, size = '8kB')),
-            "Memory to hold the nvram data")
-    # hypervisor description
-    hypervisor_desc = Param.PhysicalMemory(
-            PhysicalMemory(range = AddrRange(_hypervisor_desc_base, size = '8kB')),
-            "Memory to hold the hypervisor description")
-    # partition description
-    partition_desc = Param.PhysicalMemory(
-            PhysicalMemory(range = AddrRange(_partition_desc_base, size = '8kB')),
-            "Memory to hold the partition description")
-
-    reset_addr = Param.Addr(_rom_base, "Address to load ROM at")
-    hypervisor_addr = Param.Addr(Addr('64kB') + _rom_base,
-                                 "Address to load hypervisor at")
-    openboot_addr = Param.Addr(Addr('512kB') + _rom_base,
-                               "Address to load openboot at")
-    nvram_addr = Param.Addr(_nvram_base, "Address to put the nvram")
-    hypervisor_desc_addr = Param.Addr(_hypervisor_desc_base,
-            "Address for the hypervisor description")
-    partition_desc_addr = Param.Addr(_partition_desc_base,
-            "Address for the partition description")
-
-    reset_bin = Param.String("file that contains the reset code")
-    hypervisor_bin = Param.String("file that contains the hypervisor code")
-    openboot_bin = Param.String("file that contains the openboot code")
-    nvram_bin = Param.String("file that contains the contents of nvram")
-    hypervisor_desc_bin = Param.String("file that contains the hypervisor description")
-    partition_desc_bin = Param.String("file that contains the partition description")
-
diff --git a/src/python/m5/objects/Uart.py b/src/python/m5/objects/Uart.py
deleted file mode 100644
index 62062c6b1..000000000
--- a/src/python/m5/objects/Uart.py
+++ /dev/null
@@ -1,17 +0,0 @@
-from m5.params import *
-from m5.proxy import *
-from m5 import build_env
-from Device import BasicPioDevice
-
-class Uart(BasicPioDevice):
-    type = 'Uart'
-    abstract = True
-    sim_console = Param.SimConsole(Parent.any, "The console")
-
-class Uart8250(Uart):
-    type = 'Uart8250'
-
-if build_env['ALPHA_TLASER']:
-    class Uart8530(Uart):
-        type = 'Uart8530'
-
diff --git a/src/sim/Process.py b/src/sim/Process.py
new file mode 100644
index 000000000..16be65fd4
--- /dev/null
+++ b/src/sim/Process.py
@@ -0,0 +1,51 @@
+# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
+
+class Process(SimObject):
+    type = 'Process'
+    abstract = True
+    output = Param.String('cout', 'filename for stdout/stderr')
+    system = Param.System(Parent.any, "system process will run on")
+
+class LiveProcess(Process):
+    type = 'LiveProcess'
+    executable = Param.String('', "executable (overrides cmd[0] if set)")
+    cmd = VectorParam.String("command line (executable plus arguments)")
+    env = VectorParam.String('', "environment settings")
+    cwd = Param.String('', "current working directory")
+    input = Param.String('cin', "filename for stdin")
+    uid = Param.Int(100, 'user id')
+    euid = Param.Int(100, 'effective user id')
+    gid = Param.Int(100, 'group id')
+    egid = Param.Int(100, 'effective group id')
+    pid = Param.Int(100, 'process id')
+    ppid = Param.Int(99, 'parent process id')
diff --git a/src/sim/Root.py b/src/sim/Root.py
new file mode 100644
index 000000000..fff998e0d
--- /dev/null
+++ b/src/sim/Root.py
@@ -0,0 +1,34 @@
+# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+from m5.SimObject import SimObject
+from m5.params import *
+
+class Root(SimObject):
+    type = 'Root'
+    dummy = Param.Int(0, "We don't support objects without params")
diff --git a/src/sim/SConscript b/src/sim/SConscript
index 46dc2c8dd..50f966bcf 100644
--- a/src/sim/SConscript
+++ b/src/sim/SConscript
@@ -30,6 +30,9 @@
 
 Import('*')
 
+SimObject('Root.py')
+SimObject('System.py')
+
 Source('async.cc')
 Source('builder.cc')
 Source('core.cc')
@@ -50,5 +53,7 @@ Source('system.cc')
 if env['FULL_SYSTEM']:
     Source('pseudo_inst.cc')
 else:
+    SimObject('Process.py')
+
     Source('process.cc')
     Source('syscall_emul.cc')
diff --git a/src/sim/System.py b/src/sim/System.py
new file mode 100644
index 000000000..b37e385c1
--- /dev/null
+++ b/src/sim/System.py
@@ -0,0 +1,48 @@
+# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
+from m5 import build_env
+from PhysicalMemory import *
+
+class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing']
+
+class System(SimObject):
+    type = 'System'
+    physmem = Param.PhysicalMemory(Parent.any, "phsyical memory")
+    mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in")
+    if build_env['FULL_SYSTEM']:
+        boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
+                                             "boot processor frequency")
+        init_param = Param.UInt64(0, "numerical value to pass into simulator")
+        boot_osflags = Param.String("a", "boot flags to pass to the kernel")
+        kernel = Param.String("", "file that contains the kernel code")
+        readfile = Param.String("", "file to read startup script from")
+        symbolfile = Param.String("", "file to get the symbols from")