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| author | Lisa Hsu <hsul@eecs.umich.edu> | 2006-10-23 18:46:05 -0400 |
|---|---|---|
| committer | Lisa Hsu <hsul@eecs.umich.edu> | 2006-10-23 18:46:05 -0400 |
| commit | 764f27a0c9a6ba6008f60757769b52f5eee46ec1 (patch) | |
| tree | 9e9309da58a0a403a673d353a354308b49a3a7ea /src | |
| parent | ef8b7713ca1b6120ae4e851877f2a9ce71296219 (diff) | |
| parent | 4da3938ed99e3691cfb16c275eea659cbaaa6c30 (diff) | |
| download | gem5-764f27a0c9a6ba6008f60757769b52f5eee46ec1.tar.xz | |
Merge zizzer:/bk/newmem
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
--HG--
extra : convert_revision : bb58679e101570d50c040519fb08ffbabfee7416
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/simple/atomic.cc | 11 | ||||
| -rw-r--r-- | src/python/m5/__init__.py | 3 |
2 files changed, 7 insertions, 7 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 25c478ae9..edba55b0d 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -183,11 +183,14 @@ AtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion) void AtomicSimpleCPU::resume() { - changeState(SimObject::Running); - if (thread->status() == ThreadContext::Active) { + if (_status != SwitchedOut && _status != Idle) { assert(system->getMemoryMode() == System::Atomic); - if (!tickEvent.scheduled()) - tickEvent.schedule(curTick); + + changeState(SimObject::Running); + if (thread->status() == ThreadContext::Active) { + if (!tickEvent.scheduled()) + tickEvent.schedule(curTick); + } } } diff --git a/src/python/m5/__init__.py b/src/python/m5/__init__.py index 03e0508fb..d41fd5a61 100644 --- a/src/python/m5/__init__.py +++ b/src/python/m5/__init__.py @@ -150,7 +150,6 @@ def changeToAtomic(system): doDrain(system) print "Changing memory mode to atomic" system.changeTiming(cc_main.SimObject.Atomic) - resume(system) def changeToTiming(system): if not isinstance(system, objects.Root) and not isinstance(system, objects.System): @@ -159,7 +158,6 @@ def changeToTiming(system): doDrain(system) print "Changing memory mode to timing" system.changeTiming(cc_main.SimObject.Timing) - resume(system) def switchCpus(cpuList): print "switching cpus" @@ -190,7 +188,6 @@ def switchCpus(cpuList): cc_main.cleanupCountedDrain(drain_event) # Now all of the CPUs are ready to be switched out for old_cpu in old_cpus: - print "switching" old_cpu._ccObject.switchOut() index = 0 for new_cpu in new_cpus: |