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authorAli Saidi <Ali.Saidi@ARM.com>2012-02-01 09:48:28 -0800
committerAli Saidi <Ali.Saidi@ARM.com>2012-02-01 09:48:28 -0800
commit0a26883296597a8737a0fbf2ce4cc625d85f842c (patch)
treec5c30ab54561bbcbd388cfa8f4b308e62723615f /src
parentea8b347dc5d375572d8d19770024ec8be5fd5017 (diff)
downloadgem5-0a26883296597a8737a0fbf2ce4cc625d85f842c.tar.xz
configs: More fixes for the memory system updates
Diffstat (limited to 'src')
-rw-r--r--src/dev/arm/RealView.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index dc2219cd1..3da47399e 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -351,10 +351,11 @@ class VExpress_ELT(RealView):
def attachOnChipIO(self, bus, bridge):
self.gic.pio = bus.port
self.a9scu.pio = bus.port
+ self.local_cpu_timer.pio = bus.port
# Bridge ranges based on excluding what is part of on-chip I/O
# (gic, a9scu)
bridge.ranges = [AddrRange(self.pci_cfg_base, self.a9scu.pio_addr - 1),
- AddrRange(self.local_cpu_timer.pio_addr, Addr.max)]
+ AddrRange(self.l2x0_fake.pio_addr, Addr.max)]
# Attach I/O devices to specified bus object. Can't do this
# earlier, since the bus object itself is typically defined at the
@@ -363,7 +364,6 @@ class VExpress_ELT(RealView):
self.elba_uart.pio = bus.port
self.uart.pio = bus.port
self.realview_io.pio = bus.port
- self.local_cpu_timer.pio = bus.port
self.v2m_timer0.pio = bus.port
self.v2m_timer1.pio = bus.port
self.elba_timer0.pio = bus.port