diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2009-11-14 19:22:29 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-11-14 19:22:29 -0800 |
| commit | 812e390693253818c49585daf35692759a1c82d4 (patch) | |
| tree | 602e46f7e1c8ea902815ff1f63bd1361582d9058 /src | |
| parent | 1df0025e28d8f9699f86fc118db3b93a0f1ec50c (diff) | |
| download | gem5-812e390693253818c49585daf35692759a1c82d4.tar.xz | |
ARM: Fix up the implmentation of the mrs instruction.
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/arm/isa/decoder.isa | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/arch/arm/isa/decoder.isa b/src/arch/arm/isa/decoder.isa index 20b544a7c..cd13fa420 100644 --- a/src/arch/arm/isa/decoder.isa +++ b/src/arch/arm/isa/decoder.isa @@ -110,7 +110,9 @@ format DataOp { } 1: decode MISC_OPCODE { 0x0: decode OPCODE { - 0x8: PredOp::mrs_cpsr({{ Rd = Cpsr | CondCodes; }}); + 0x8: PredOp::mrs_cpsr({{ + Rd = (Cpsr | CondCodes) & 0xF8FF03DF; + }}); 0x9: PredOp::msr_cpsr({{ //assert(!RN<1:0>); if (OPCODE_18) { @@ -120,7 +122,7 @@ format DataOp { CondCodes = mbits(Rm, 31,27); } }}); - 0xa: PredOp::mrs_spsr({{ Rd = 0; // should be SPSR}}); + 0xa: PredOp::mrs_spsr({{ Rd = Spsr; }}); 0xb: WarnUnimpl::msr_spsr(); } 0x1: decode OPCODE { |