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authorGabe Black <gabeblack@google.com>2019-11-05 15:53:02 -0800
committerGabe Black <gabeblack@google.com>2019-12-27 20:52:13 +0000
commit09b658f69969ef998b5994156f92f7b645aaf619 (patch)
treeaa49e0dc7771ce18e89a7dc66e07b8fa356b2f7b /src
parent1a71417b89f20f5637f60b6a032f8ba9cfc95378 (diff)
downloadgem5-09b658f69969ef998b5994156f92f7b645aaf619.tar.xz
fastmodel: Checkpoint the TCs when checkpointing a fast model CPU.
The generic thread context checkpointing code can be used which calls into the ThreadContext methods to read the required state. Change-Id: Ib5c318ff4d2e756274b4c90b56533b2689a837f2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23785 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Diffstat (limited to 'src')
-rw-r--r--src/arch/arm/fastmodel/iris/cpu.cc7
-rw-r--r--src/arch/arm/fastmodel/iris/cpu.hh2
2 files changed, 9 insertions, 0 deletions
diff --git a/src/arch/arm/fastmodel/iris/cpu.cc b/src/arch/arm/fastmodel/iris/cpu.cc
index e5d95ef65..6c282b69a 100644
--- a/src/arch/arm/fastmodel/iris/cpu.cc
+++ b/src/arch/arm/fastmodel/iris/cpu.cc
@@ -31,6 +31,7 @@
#include "arch/arm/fastmodel/iris/thread_context.hh"
#include "scx/scx.h"
+#include "sim/serialize.hh"
namespace Iris
{
@@ -93,4 +94,10 @@ BaseCPU::init()
tc->initMemProxies(tc);
}
+void
+BaseCPU::serializeThread(CheckpointOut &cp, ThreadID tid) const
+{
+ ::serialize(*threadContexts[tid], cp);
+}
+
} // namespace Iris
diff --git a/src/arch/arm/fastmodel/iris/cpu.hh b/src/arch/arm/fastmodel/iris/cpu.hh
index 0d15fc82a..3b913b92d 100644
--- a/src/arch/arm/fastmodel/iris/cpu.hh
+++ b/src/arch/arm/fastmodel/iris/cpu.hh
@@ -118,6 +118,8 @@ class BaseCPU : public ::BaseCPU
}
void init() override;
+
+ void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
};
// This class specializes the one above and sets up ThreadContexts based on