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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:15 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:15 -0500 |
| commit | 2d08b8de9166552a3214012ecdfb98bd8fd3eafb (patch) | |
| tree | 612c5e35345bbd2e28e084abbc5ece3d1a236deb /src | |
| parent | 57c4d37c102e2fb4d1c86fe1d583ee67c76945b1 (diff) | |
| download | gem5-2d08b8de9166552a3214012ecdfb98bd8fd3eafb.tar.xz | |
ARM: Implement the version of VMRS that writes to the APSR.
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/arm/isa/formats/fp.isa | 12 | ||||
| -rw-r--r-- | src/arch/arm/isa/includes.isa | 1 | ||||
| -rw-r--r-- | src/arch/arm/isa/insts/fp.isa | 8 |
3 files changed, 20 insertions, 1 deletions
diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa index 83f541584..284876311 100644 --- a/src/arch/arm/isa/formats/fp.isa +++ b/src/arch/arm/isa/formats/fp.isa @@ -409,7 +409,17 @@ let {{ default: return new Unknown(machInst); } - return new Vmrs(machInst, rt, (IntRegIndex)specReg); + if (rt == 0xf) { + CPSR cpsrMask = 0; + cpsrMask.n = 1; + cpsrMask.z = 1; + cpsrMask.c = 1; + cpsrMask.v = 1; + return new VmrsApsr(machInst, INTREG_CONDCODES, + (IntRegIndex)specReg, (uint32_t)cpsrMask); + } else { + return new Vmrs(machInst, rt, (IntRegIndex)specReg); + } } } else { uint32_t vd = (bits(machInst, 7) << 5) | diff --git a/src/arch/arm/isa/includes.isa b/src/arch/arm/isa/includes.isa index e3e345c74..b3ad567dc 100644 --- a/src/arch/arm/isa/includes.isa +++ b/src/arch/arm/isa/includes.isa @@ -63,6 +63,7 @@ output header {{ output decoder {{ #include "arch/arm/faults.hh" +#include "arch/arm/intregs.hh" #include "arch/arm/isa_traits.hh" #include "arch/arm/utility.hh" #include "base/cprintf.hh" diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa index 0abae6a20..c5ce813f9 100644 --- a/src/arch/arm/isa/insts/fp.isa +++ b/src/arch/arm/isa/insts/fp.isa @@ -205,6 +205,14 @@ let {{ decoder_output += VfpRegRegOpConstructor.subst(vmrsIop); exec_output += PredOpExecute.subst(vmrsIop); + vmrsApsrCode = "Dest = (MiscOp1 & imm) | (Dest & ~imm);" + vmrsApsrIop = InstObjParams("vmrs", "VmrsApsr", "VfpRegRegImmOp", + { "code": vmrsApsrCode, + "predicate_test": predicateTest }, []) + header_output += VfpRegRegImmOpDeclare.subst(vmrsApsrIop); + decoder_output += VfpRegRegImmOpConstructor.subst(vmrsApsrIop); + exec_output += PredOpExecute.subst(vmrsApsrIop); + vmovImmSCode = ''' FpDest.uw = bits(imm, 31, 0); ''' |