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author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-19 10:35:14 -0400 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-19 10:35:14 -0400 |
commit | 619c5519fe214250d537527ec95191a9b3d6fad2 (patch) | |
tree | 2e6471bc3df41633665beb552809ac6cc9801e30 /src | |
parent | 586a219d11e988d392efe7c34d27bd00d1dedf43 (diff) | |
download | gem5-619c5519fe214250d537527ec95191a9b3d6fad2.tar.xz |
cpu: Use a deque in o3 rename instruction queue
Switch from a list to a data structure with better data layout.
Diffstat (limited to 'src')
-rw-r--r-- | src/cpu/o3/rename.hh | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/src/cpu/o3/rename.hh b/src/cpu/o3/rename.hh index 89bf0608f..a543cefb8 100644 --- a/src/cpu/o3/rename.hh +++ b/src/cpu/o3/rename.hh @@ -86,12 +86,11 @@ class DefaultRename // Typedefs from the ISA. typedef TheISA::RegIndex RegIndex; - // A list is used to queue the instructions. Barrier insts must - // be added to the front of the list, which is the only reason for - // using a list instead of a queue. (Most other stages use a + // A deque is used to queue the instructions. Barrier insts must + // be added to the front of the queue, which is the only reason for + // using a deque instead of a queue. (Most other stages use a // queue) - typedef std::list<DynInstPtr> InstQueue; - typedef typename std::list<DynInstPtr>::iterator ListIt; + typedef std::deque<DynInstPtr> InstQueue; public: /** Overall rename status. Used to determine if the CPU can |