cpu: Eliminate the ProxyThreadContext class.

Replace it with direct inheritance from the ThreadContext class in the
SimpleThread class which was the only place it was used.

Also take the opportunity to use some specialized types instead of
ints, etc., add some consts, and fix some style issues.

Change-Id: I5d2cfa87b20dc43615e33e6755c9d016564e9c0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18048
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

9 files changed, 641 insertions, 709 deletions

diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 197bb16ea..bac8e8d48 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -492,7 +492,7 @@ SimpleThread::hwrei()
     pc.npc(readMiscRegNoEffect(IPR_EXC_ADDR));
     pcState(pc);
 
-    CPA::cpa()->swAutoBegin(tc, pc.npc());
+    CPA::cpa()->swAutoBegin(this, pc.npc());
 
     if (kernelStats)
         kernelStats->hwrei();
@@ -509,7 +509,7 @@ bool
 SimpleThread::simPalCheck(int palFunc)
 {
     if (kernelStats)
-        kernelStats->callpal(palFunc, tc);
+        kernelStats->callpal(palFunc, this);
 
     switch (palFunc) {
       case PAL::halt:
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index d88c9b250..26973cdbf 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -98,7 +98,8 @@ class CheckerThreadContext : public ThreadContext
 
     ContextID contextId() const override { return actualTC->contextId(); }
 
-    void setContextId(ContextID id)override
+    void
+    setContextId(ContextID id) override
     {
        actualTC->setContextId(id);
        checkerTC->setContextId(id);
@@ -106,7 +107,8 @@ class CheckerThreadContext : public ThreadContext
 
     /** Returns this thread's ID number. */
     int threadId() const override { return actualTC->threadId(); }
-    void setThreadId(int id) override
+    void
+    setThreadId(int id) override
     {
         checkerTC->setThreadId(id);
         actualTC->setThreadId(id);
@@ -116,21 +118,27 @@ class CheckerThreadContext : public ThreadContext
 
     BaseTLB *getDTBPtr() override { return actualTC->getDTBPtr(); }
 
-    CheckerCPU *getCheckerCpuPtr()override
+    CheckerCPU *
+    getCheckerCpuPtr() override
     {
         return checkerCPU;
     }
 
     TheISA::ISA *getIsaPtr() override { return actualTC->getIsaPtr(); }
 
-    TheISA::Decoder *getDecoderPtr() override {
+    TheISA::Decoder *
+    getDecoderPtr() override
+    {
         return actualTC->getDecoderPtr();
     }
 
     System *getSystemPtr() override { return actualTC->getSystemPtr(); }
 
-    TheISA::Kernel::Statistics *getKernelStats()override
-    { return actualTC->getKernelStats(); }
+    TheISA::Kernel::Statistics *
+    getKernelStats() override
+    {
+        return actualTC->getKernelStats();
+    }
 
     Process *getProcessPtr() override { return actualTC->getProcessPtr(); }
 
@@ -138,28 +146,41 @@ class CheckerThreadContext : public ThreadContext
 
     PortProxy &getPhysProxy() override { return actualTC->getPhysProxy(); }
 
-    FSTranslatingPortProxy &getVirtProxy() override
-    { return actualTC->getVirtProxy(); }
+    FSTranslatingPortProxy &
+    getVirtProxy() override
+    {
+        return actualTC->getVirtProxy();
+    }
 
-    void initMemProxies(ThreadContext *tc) override
-    { actualTC->initMemProxies(tc); }
+    void
+    initMemProxies(ThreadContext *tc) override
+    {
+        actualTC->initMemProxies(tc);
+    }
 
-    void connectMemPorts(ThreadContext *tc)
+    void
+    connectMemPorts(ThreadContext *tc)
     {
         actualTC->connectMemPorts(tc);
     }
 
-    SETranslatingPortProxy &getMemProxy() override {
+    SETranslatingPortProxy &
+    getMemProxy() override
+    {
         return actualTC->getMemProxy();
     }
 
     /** Executes a syscall in SE mode. */
-    void syscall(int64_t callnum, Fault *fault)override
-    { return actualTC->syscall(callnum, fault); }
+    void
+    syscall(int64_t callnum, Fault *fault) override
+    {
+        return actualTC->syscall(callnum, fault);
+    }
 
     Status status() const override { return actualTC->status(); }
 
-    void setStatus(Status new_status) override
+    void
+    setStatus(Status new_status) override
     {
         actualTC->setStatus(new_status);
         checkerTC->setStatus(new_status);
@@ -169,43 +190,49 @@ class CheckerThreadContext : public ThreadContext
     void activate() override { actualTC->activate(); }
 
     /// Set the status to Suspended.
-    void suspend() override{ actualTC->suspend(); }
+    void suspend() override { actualTC->suspend(); }
 
     /// Set the status to Halted.
-    void halt() override{ actualTC->halt(); }
+    void halt() override { actualTC->halt(); }
 
-    void dumpFuncProfile()  override{ actualTC->dumpFuncProfile(); }
+    void dumpFuncProfile() override { actualTC->dumpFuncProfile(); }
 
-    void takeOverFrom(ThreadContext *oldContext) override
+    void
+    takeOverFrom(ThreadContext *oldContext) override
     {
         actualTC->takeOverFrom(oldContext);
         checkerTC->copyState(oldContext);
     }
 
-    void regStats(const std::string &name) override
+    void
+    regStats(const std::string &name) override
     {
         actualTC->regStats(name);
         checkerTC->regStats(name);
     }
 
-    EndQuiesceEvent *getQuiesceEvent() override {
+    EndQuiesceEvent *
+    getQuiesceEvent() override
+    {
         return actualTC->getQuiesceEvent();
     }
 
-    Tick readLastActivate()  override{ return actualTC->readLastActivate(); }
-    Tick readLastSuspend()  override{ return actualTC->readLastSuspend(); }
+    Tick readLastActivate() override { return actualTC->readLastActivate(); }
+    Tick readLastSuspend() override { return actualTC->readLastSuspend(); }
 
-    void profileClear()  override{ return actualTC->profileClear(); }
-    void profileSample()  override{ return actualTC->profileSample(); }
+    void profileClear() override { return actualTC->profileClear(); }
+    void profileSample() override { return actualTC->profileSample(); }
 
     // @todo: Do I need this?
-    void copyArchRegs(ThreadContext *tc) override
+    void
+    copyArchRegs(ThreadContext *tc) override
     {
         actualTC->copyArchRegs(tc);
         checkerTC->copyArchRegs(tc);
     }
 
-    void clearArchRegs() override
+    void
+    clearArchRegs() override
     {
         actualTC->clearArchRegs();
         checkerTC->clearArchRegs();
@@ -214,83 +241,123 @@ class CheckerThreadContext : public ThreadContext
     //
     // New accessors for new decoder.
     //
-    RegVal readIntReg(int reg_idx) override {
+    RegVal
+    readIntReg(RegIndex reg_idx) const override
+    {
         return actualTC->readIntReg(reg_idx);
     }
 
     RegVal
-    readFloatReg(int reg_idx) override
+    readFloatReg(RegIndex reg_idx) const override
     {
         return actualTC->readFloatReg(reg_idx);
     }
 
-    const VecRegContainer& readVecReg (const RegId& reg) const override
-    { return actualTC->readVecReg(reg); }
+    const VecRegContainer &
+    readVecReg (const RegId &reg) const override
+    {
+        return actualTC->readVecReg(reg);
+    }
 
     /**
      * Read vector register for modification, hierarchical indexing.
      */
-    VecRegContainer& getWritableVecReg (const RegId& reg) override
-    { return actualTC->getWritableVecReg(reg); }
+    VecRegContainer &
+    getWritableVecReg (const RegId &reg) override
+    {
+        return actualTC->getWritableVecReg(reg);
+    }
 
     /** Vector Register Lane Interfaces. */
     /** @{ */
     /** Reads source vector 8bit operand. */
     ConstVecLane8
-    readVec8BitLaneReg(const RegId& reg) const override
-    { return actualTC->readVec8BitLaneReg(reg); }
+    readVec8BitLaneReg(const RegId &reg) const override
+    {
+        return actualTC->readVec8BitLaneReg(reg);
+    }
 
     /** Reads source vector 16bit operand. */
     ConstVecLane16
-    readVec16BitLaneReg(const RegId& reg) const override
-    { return actualTC->readVec16BitLaneReg(reg); }
+    readVec16BitLaneReg(const RegId &reg) const override
+    {
+        return actualTC->readVec16BitLaneReg(reg);
+    }
 
     /** Reads source vector 32bit operand. */
     ConstVecLane32
-    readVec32BitLaneReg(const RegId& reg) const override
-    { return actualTC->readVec32BitLaneReg(reg); }
+    readVec32BitLaneReg(const RegId &reg) const override
+    {
+        return actualTC->readVec32BitLaneReg(reg);
+    }
 
     /** Reads source vector 64bit operand. */
     ConstVecLane64
-    readVec64BitLaneReg(const RegId& reg) const override
-    { return actualTC->readVec64BitLaneReg(reg); }
+    readVec64BitLaneReg(const RegId &reg) const override
+    {
+        return actualTC->readVec64BitLaneReg(reg);
+    }
 
     /** Write a lane of the destination vector register. */
-    virtual void setVecLane(const RegId& reg,
-            const LaneData<LaneSize::Byte>& val) override
-    { return actualTC->setVecLane(reg, val); }
-    virtual void setVecLane(const RegId& reg,
-            const LaneData<LaneSize::TwoByte>& val) override
-    { return actualTC->setVecLane(reg, val); }
-    virtual void setVecLane(const RegId& reg,
-            const LaneData<LaneSize::FourByte>& val) override
-    { return actualTC->setVecLane(reg, val); }
-    virtual void setVecLane(const RegId& reg,
-            const LaneData<LaneSize::EightByte>& val) override
-    { return actualTC->setVecLane(reg, val); }
+    virtual void
+    setVecLane(const RegId &reg,
+               const LaneData<LaneSize::Byte> &val) override
+    {
+        return actualTC->setVecLane(reg, val);
+    }
+    virtual void
+    setVecLane(const RegId &reg,
+               const LaneData<LaneSize::TwoByte> &val) override
+    {
+        return actualTC->setVecLane(reg, val);
+    }
+    virtual void
+    setVecLane(const RegId &reg,
+               const LaneData<LaneSize::FourByte> &val) override
+    {
+        return actualTC->setVecLane(reg, val);
+    }
+    virtual void
+    setVecLane(const RegId &reg,
+               const LaneData<LaneSize::EightByte> &val) override
+    {
+        return actualTC->setVecLane(reg, val);
+    }
     /** @} */
 
-    const VecElem& readVecElem(const RegId& reg) const override
-    { return actualTC->readVecElem(reg); }
+    const VecElem &
+    readVecElem(const RegId& reg) const override
+    {
+        return actualTC->readVecElem(reg);
+    }
 
-    const VecPredRegContainer& readVecPredReg(const RegId& reg) const override
-    { return actualTC->readVecPredReg(reg); }
+    const VecPredRegContainer &
+    readVecPredReg(const RegId& reg) const override
+    {
+        return actualTC->readVecPredReg(reg);
+    }
 
-    VecPredRegContainer& getWritableVecPredReg(const RegId& reg) override
-    { return actualTC->getWritableVecPredReg(reg); }
+    VecPredRegContainer &
+    getWritableVecPredReg(const RegId& reg) override
+    {
+        return actualTC->getWritableVecPredReg(reg);
+    }
 
-    RegVal readCCReg(int reg_idx) override
-    { return actualTC->readCCReg(reg_idx); }
+    RegVal
+    readCCReg(RegIndex reg_idx) const override
+    {
+        return actualTC->readCCReg(reg_idx);
+    }
 
     void
-    setIntReg(int reg_idx, RegVal val) override
+    setIntReg(RegIndex reg_idx, RegVal val) override
     {
         actualTC->setIntReg(reg_idx, val);
         checkerTC->setIntReg(reg_idx, val);
     }
 
     void
-    setFloatReg(int reg_idx, RegVal val) override
+    setFloatReg(RegIndex reg_idx, RegVal val) override
     {
         actualTC->setFloatReg(reg_idx, val);
         checkerTC->setFloatReg(reg_idx, val);
@@ -318,15 +385,14 @@ class CheckerThreadContext : public ThreadContext
     }
 
     void
-    setCCReg(int reg_idx, RegVal val) override
+    setCCReg(RegIndex reg_idx, RegVal val) override
     {
         actualTC->setCCReg(reg_idx, val);
         checkerTC->setCCReg(reg_idx, val);
     }
 
     /** Reads this thread's PC state. */
-    TheISA::PCState pcState() override
-    { return actualTC->pcState(); }
+    TheISA::PCState pcState() const override { return actualTC->pcState(); }
 
     /** Sets this thread's PC state. */
     void
@@ -353,25 +419,28 @@ class CheckerThreadContext : public ThreadContext
     }
 
     /** Reads this thread's PC. */
-    Addr instAddr() override
-    { return actualTC->instAddr(); }
+    Addr instAddr() const override { return actualTC->instAddr(); }
 
     /** Reads this thread's next PC. */
-    Addr nextInstAddr() override
-    { return actualTC->nextInstAddr(); }
+    Addr nextInstAddr() const override { return actualTC->nextInstAddr(); }
 
     /** Reads this thread's next PC. */
-    MicroPC microPC() override
-    { return actualTC->microPC(); }
+    MicroPC microPC() const override { return actualTC->microPC(); }
 
-    RegVal readMiscRegNoEffect(int misc_reg) const override
-    { return actualTC->readMiscRegNoEffect(misc_reg); }
+    RegVal
+    readMiscRegNoEffect(RegIndex misc_reg) const override
+    {
+        return actualTC->readMiscRegNoEffect(misc_reg);
+    }
 
-    RegVal readMiscReg(int misc_reg) override
-    { return actualTC->readMiscReg(misc_reg); }
+    RegVal
+    readMiscReg(RegIndex misc_reg) override
+    {
+        return actualTC->readMiscReg(misc_reg);
+    }
 
     void
-    setMiscRegNoEffect(int misc_reg, RegVal val) override
+    setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
     {
         DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
                          " and O3..\n", misc_reg);
@@ -380,7 +449,7 @@ class CheckerThreadContext : public ThreadContext
     }
 
     void
-    setMiscReg(int misc_reg, RegVal val) override
+    setMiscReg(RegIndex misc_reg, RegVal val) override
     {
         DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
                          " and O3..\n", misc_reg);
@@ -394,8 +463,11 @@ class CheckerThreadContext : public ThreadContext
         return actualTC->flattenRegId(regId);
     }
 
-    unsigned readStCondFailures() override
-    { return actualTC->readStCondFailures(); }
+    unsigned
+    readStCondFailures() const override
+    {
+        return actualTC->readStCondFailures();
+    }
 
     void
     setStCondFailures(unsigned sc_failures) override
@@ -403,32 +475,38 @@ class CheckerThreadContext : public ThreadContext
         actualTC->setStCondFailures(sc_failures);
     }
 
-    Counter readFuncExeInst() override { return actualTC->readFuncExeInst(); }
+    Counter
+    readFuncExeInst() const override
+    {
+        return actualTC->readFuncExeInst();
+    }
 
-    RegVal readIntRegFlat(int idx) override {
+    RegVal
+    readIntRegFlat(RegIndex idx) const override
+    {
         return actualTC->readIntRegFlat(idx);
     }
 
     void
-    setIntRegFlat(int idx, RegVal val) override
+    setIntRegFlat(RegIndex idx, RegVal val) override
     {
         actualTC->setIntRegFlat(idx, val);
     }
 
     RegVal
-    readFloatRegFlat(int idx) override
+    readFloatRegFlat(RegIndex idx) const override
     {
         return actualTC->readFloatRegFlat(idx);
     }
 
     void
-    setFloatRegFlat(int idx, RegVal val) override
+    setFloatRegFlat(RegIndex idx, RegVal val) override
     {
         actualTC->setFloatRegFlat(idx, val);
     }
 
     const VecRegContainer &
-    readVecRegFlat(int idx) const override
+    readVecRegFlat(RegIndex idx) const override
     {
         return actualTC->readVecRegFlat(idx);
     }
@@ -437,36 +515,59 @@ class CheckerThreadContext : public ThreadContext
      * Read vector register for modification, flat indexing.
      */
     VecRegContainer &
-    getWritableVecRegFlat(int idx) override
+    getWritableVecRegFlat(RegIndex idx) override
     {
         return actualTC->getWritableVecRegFlat(idx);
     }
 
-    void setVecRegFlat(int idx, const VecRegContainer& val) override
-    { actualTC->setVecRegFlat(idx, val); }
+    void
+    setVecRegFlat(RegIndex idx, const VecRegContainer& val) override
+    {
+        actualTC->setVecRegFlat(idx, val);
+    }
 
-    const VecElem& readVecElemFlat(const RegIndex& idx,
-                                   const ElemIndex& elem_idx) const override
-    { return actualTC->readVecElemFlat(idx, elem_idx); }
+    const VecElem &
+    readVecElemFlat(RegIndex idx, const ElemIndex& elem_idx) const override
+    {
+        return actualTC->readVecElemFlat(idx, elem_idx);
+    }
 
-    void setVecElemFlat(const RegIndex& idx,
-                        const ElemIndex& elem_idx, const VecElem& val) override
-    { actualTC->setVecElemFlat(idx, elem_idx, val); }
+    void
+    setVecElemFlat(RegIndex idx,
+                   const ElemIndex& elem_idx, const VecElem& val) override
+    {
+        actualTC->setVecElemFlat(idx, elem_idx, val);
+    }
 
-    const VecPredRegContainer& readVecPredRegFlat(int idx) const override
-    { return actualTC->readVecPredRegFlat(idx); }
+    const VecPredRegContainer &
+    readVecPredRegFlat(RegIndex idx) const override
+    {
+        return actualTC->readVecPredRegFlat(idx);
+    }
 
-    VecPredRegContainer& getWritableVecPredRegFlat(int idx) override
-    { return actualTC->getWritableVecPredRegFlat(idx); }
+    VecPredRegContainer &
+    getWritableVecPredRegFlat(RegIndex idx) override
+    {
+        return actualTC->getWritableVecPredRegFlat(idx);
+    }
 
-    void setVecPredRegFlat(int idx, const VecPredRegContainer& val) override
-    { actualTC->setVecPredRegFlat(idx, val); }
+    void
+    setVecPredRegFlat(RegIndex idx, const VecPredRegContainer& val) override
+    {
+        actualTC->setVecPredRegFlat(idx, val);
+    }
 
-    RegVal readCCRegFlat(int idx) override
-    { return actualTC->readCCRegFlat(idx); }
+    RegVal
+    readCCRegFlat(RegIndex idx) const override
+    {
+        return actualTC->readCCRegFlat(idx);
+    }
 
-    void setCCRegFlat(int idx, RegVal val) override
-    { actualTC->setCCRegFlat(idx, val); }
+    void
+    setCCRegFlat(RegIndex idx, RegVal val) override
+    {
+        actualTC->setCCRegFlat(idx, val);
+    }
 };
 
 #endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 374ef377d..b87aac4a7 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -99,115 +99,121 @@ class O3ThreadContext : public ThreadContext
     }
 
     /** Returns a pointer to this CPU. */
-    virtual BaseCPU *getCpuPtr() override { return cpu; }
+    BaseCPU *getCpuPtr() override { return cpu; }
 
     /** Reads this CPU's ID. */
-    virtual int cpuId() const override { return cpu->cpuId(); }
+    int cpuId() const override { return cpu->cpuId(); }
 
     /** Reads this CPU's Socket ID. */
-    virtual uint32_t socketId() const override { return cpu->socketId(); }
+    uint32_t socketId() const override { return cpu->socketId(); }
 
-    virtual ContextID
-    contextId() const override { return thread->contextId(); }
+    ContextID contextId() const override { return thread->contextId(); }
 
-    virtual void setContextId(int id) override { thread->setContextId(id); }
+    void setContextId(ContextID id) override { thread->setContextId(id); }
 
     /** Returns this thread's ID number. */
-    virtual int threadId() const override
-    { return thread->threadId(); }
-    virtual void setThreadId(int id) override
-    { return thread->setThreadId(id); }
+    int threadId() const override { return thread->threadId(); }
+    void setThreadId(int id) override { return thread->setThreadId(id); }
 
     /** Returns a pointer to the system. */
-    virtual System *getSystemPtr() override { return cpu->system; }
+    System *getSystemPtr() override { return cpu->system; }
 
     /** Returns a pointer to this thread's kernel statistics. */
-    virtual TheISA::Kernel::Statistics *getKernelStats() override
-    { return thread->kernelStats; }
+    TheISA::Kernel::Statistics *
+    getKernelStats() override
+    {
+        return thread->kernelStats;
+    }
 
     /** Returns a pointer to this thread's process. */
-    virtual Process *getProcessPtr() override
-    { return thread->getProcessPtr(); }
+    Process *getProcessPtr() override { return thread->getProcessPtr(); }
 
-    virtual void setProcessPtr(Process *p) override
-    { thread->setProcessPtr(p); }
+    void setProcessPtr(Process *p) override { thread->setProcessPtr(p); }
 
-    virtual PortProxy &getPhysProxy() override
-    { return thread->getPhysProxy(); }
+    PortProxy &getPhysProxy() override { return thread->getPhysProxy(); }
 
-    virtual FSTranslatingPortProxy &getVirtProxy() override;
+    FSTranslatingPortProxy &getVirtProxy() override;
 
-    virtual void initMemProxies(ThreadContext *tc) override
-    { thread->initMemProxies(tc); }
+    void
+    initMemProxies(ThreadContext *tc) override
+    {
+        thread->initMemProxies(tc);
+    }
 
-    virtual SETranslatingPortProxy &getMemProxy() override
-    { return thread->getMemProxy(); }
+    SETranslatingPortProxy &
+    getMemProxy() override
+    {
+        return thread->getMemProxy();
+    }
 
     /** Returns this thread's status. */
-    virtual Status status() const override { return thread->status(); }
+    Status status() const override { return thread->status(); }
 
     /** Sets this thread's status. */
-    virtual void setStatus(Status new_status) override
-    { thread->setStatus(new_status); }
+    void
+    setStatus(Status new_status) override
+    {
+        thread->setStatus(new_status);
+    }
 
     /** Set the status to Active. */
-    virtual void activate() override;
+    void activate() override;
 
     /** Set the status to Suspended. */
-    virtual void suspend() override;
+    void suspend() override;
 
     /** Set the status to Halted. */
-    virtual void halt() override;
+    void halt() override;
 
     /** Dumps the function profiling information.
      * @todo: Implement.
      */
-    virtual void dumpFuncProfile() override;
+    void dumpFuncProfile() override;
 
     /** Takes over execution of a thread from another CPU. */
-    virtual void takeOverFrom(ThreadContext *old_context) override;
+    void takeOverFrom(ThreadContext *old_context) override;
 
     /** Registers statistics associated with this TC. */
-    virtual void regStats(const std::string &name) override;
+    void regStats(const std::string &name) override;
 
     /** Reads the last tick that this thread was activated on. */
-    virtual Tick readLastActivate() override;
+    Tick readLastActivate() override;
     /** Reads the last tick that this thread was suspended on. */
-    virtual Tick readLastSuspend() override;
+    Tick readLastSuspend() override;
 
     /** Clears the function profiling information. */
-    virtual void profileClear() override;
+    void profileClear() override;
     /** Samples the function profiling information. */
-    virtual void profileSample() override;
+    void profileSample() override;
 
     /** Copies the architectural registers from another TC into this TC. */
-    virtual void copyArchRegs(ThreadContext *tc) override;
+    void copyArchRegs(ThreadContext *tc) override;
 
     /** Resets all architectural registers to 0. */
-    virtual void clearArchRegs() override;
+    void clearArchRegs() override;
 
     /** Reads an integer register. */
-    virtual RegVal
-    readReg(int reg_idx)
+    RegVal
+    readReg(RegIndex reg_idx)
     {
         return readIntRegFlat(flattenRegId(RegId(IntRegClass,
                                                  reg_idx)).index());
     }
-    virtual RegVal
-    readIntReg(int reg_idx) override
+    RegVal
+    readIntReg(RegIndex reg_idx) const override
     {
         return readIntRegFlat(flattenRegId(RegId(IntRegClass,
                                                  reg_idx)).index());
     }
 
-    virtual RegVal
-    readFloatReg(int reg_idx) override
+    RegVal
+    readFloatReg(RegIndex reg_idx) const override
     {
         return readFloatRegFlat(flattenRegId(RegId(FloatRegClass,
                                              reg_idx)).index());
     }
 
-    virtual const VecRegContainer &
+    const VecRegContainer &
     readVecReg(const RegId& id) const override
     {
         return readVecRegFlat(flattenRegId(id).index());
@@ -216,7 +222,7 @@ class O3ThreadContext : public ThreadContext
     /**
      * Read vector register operand for modification, hierarchical indexing.
      */
-    virtual VecRegContainer &
+    VecRegContainer &
     getWritableVecReg(const RegId& id) override
     {
         return getWritableVecRegFlat(flattenRegId(id).index());
@@ -225,7 +231,7 @@ class O3ThreadContext : public ThreadContext
     /** Vector Register Lane Interfaces. */
     /** @{ */
     /** Reads source vector 8bit operand. */
-    virtual ConstVecLane8
+    ConstVecLane8
     readVec8BitLaneReg(const RegId& id) const override
     {
         return readVecLaneFlat<uint8_t>(flattenRegId(id).index(),
@@ -233,7 +239,7 @@ class O3ThreadContext : public ThreadContext
     }
 
     /** Reads source vector 16bit operand. */
-    virtual ConstVecLane16
+    ConstVecLane16
     readVec16BitLaneReg(const RegId& id) const override
     {
         return readVecLaneFlat<uint16_t>(flattenRegId(id).index(),
@@ -241,7 +247,7 @@ class O3ThreadContext : public ThreadContext
     }
 
     /** Reads source vector 32bit operand. */
-    virtual ConstVecLane32
+    ConstVecLane32
     readVec32BitLaneReg(const RegId& id) const override
     {
         return readVecLaneFlat<uint32_t>(flattenRegId(id).index(),
@@ -249,7 +255,7 @@ class O3ThreadContext : public ThreadContext
     }
 
     /** Reads source vector 64bit operand. */
-    virtual ConstVecLane64
+    ConstVecLane64
     readVec64BitLaneReg(const RegId& id) const override
     {
         return readVecLaneFlat<uint64_t>(flattenRegId(id).index(),
@@ -257,137 +263,180 @@ class O3ThreadContext : public ThreadContext
     }
 
     /** Write a lane of the destination vector register. */
-    virtual void setVecLane(const RegId& reg,
-            const LaneData<LaneSize::Byte>& val) override
-    { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); }
-    virtual void setVecLane(const RegId& reg,
-            const LaneData<LaneSize::TwoByte>& val) override
-    { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); }
-    virtual void setVecLane(const RegId& reg,
-            const LaneData<LaneSize::FourByte>& val) override
-    { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); }
-    virtual void setVecLane(const RegId& reg,
-            const LaneData<LaneSize::EightByte>& val) override
-    { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); }
+    void
+    setVecLane(const RegId& reg,
+               const LaneData<LaneSize::Byte>& val) override
+    {
+        return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
+    }
+    void
+    setVecLane(const RegId& reg,
+               const LaneData<LaneSize::TwoByte>& val) override
+    {
+        return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
+    }
+    void
+    setVecLane(const RegId& reg,
+               const LaneData<LaneSize::FourByte>& val) override
+    {
+        return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
+    }
+    void
+    setVecLane(const RegId& reg,
+               const LaneData<LaneSize::EightByte>& val) override
+    {
+        return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
+    }
     /** @} */
 
-    virtual const VecElem& readVecElem(const RegId& reg) const override {
+    const VecElem &
+    readVecElem(const RegId& reg) const override
+    {
         return readVecElemFlat(flattenRegId(reg).index(), reg.elemIndex());
     }
 
-    virtual const VecPredRegContainer&
-    readVecPredReg(const RegId& id) const override {
+    const VecPredRegContainer &
+    readVecPredReg(const RegId& id) const override
+    {
         return readVecPredRegFlat(flattenRegId(id).index());
     }
 
-    virtual VecPredRegContainer&
-    getWritableVecPredReg(const RegId& id) override {
+    VecPredRegContainer&
+    getWritableVecPredReg(const RegId& id) override
+    {
         return getWritableVecPredRegFlat(flattenRegId(id).index());
     }
 
-    virtual RegVal
-    readCCReg(int reg_idx) override
+    RegVal
+    readCCReg(RegIndex reg_idx) const override
     {
         return readCCRegFlat(flattenRegId(RegId(CCRegClass,
                                                  reg_idx)).index());
     }
 
     /** Sets an integer register to a value. */
-    virtual void
-    setIntReg(int reg_idx, RegVal val) override
+    void
+    setIntReg(RegIndex reg_idx, RegVal val) override
     {
         setIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index(), val);
     }
 
-    virtual void
-    setFloatReg(int reg_idx, RegVal val) override
+    void
+    setFloatReg(RegIndex reg_idx, RegVal val) override
     {
         setFloatRegFlat(flattenRegId(RegId(FloatRegClass,
                                            reg_idx)).index(), val);
     }
 
-    virtual void
+    void
     setVecReg(const RegId& reg, const VecRegContainer& val) override
     {
         setVecRegFlat(flattenRegId(reg).index(), val);
     }
 
-    virtual void
+    void
     setVecElem(const RegId& reg, const VecElem& val) override
     {
         setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
     }
 
-    virtual void
+    void
     setVecPredReg(const RegId& reg,
                   const VecPredRegContainer& val) override
     {
         setVecPredRegFlat(flattenRegId(reg).index(), val);
     }
 
-    virtual void
-    setCCReg(int reg_idx, RegVal val) override
+    void
+    setCCReg(RegIndex reg_idx, RegVal val) override
     {
         setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val);
     }
 
     /** Reads this thread's PC state. */
-    virtual TheISA::PCState pcState() override
-    { return cpu->pcState(thread->threadId()); }
+    TheISA::PCState
+    pcState() const override
+    {
+        return cpu->pcState(thread->threadId());
+    }
 
     /** Sets this thread's PC state. */
-    virtual void pcState(const TheISA::PCState &val) override;
+    void pcState(const TheISA::PCState &val) override;
 
-    virtual void pcStateNoRecord(const TheISA::PCState &val) override;
+    void pcStateNoRecord(const TheISA::PCState &val) override;
 
     /** Reads this thread's PC. */
-    virtual Addr instAddr() override
-    { return cpu->instAddr(thread->threadId()); }
+    Addr
+    instAddr() const override
+    {
+        return cpu->instAddr(thread->threadId());
+    }
 
     /** Reads this thread's next PC. */
-    virtual Addr nextInstAddr() override
-    { return cpu->nextInstAddr(thread->threadId()); }
+    Addr
+    nextInstAddr() const override
+    {
+        return cpu->nextInstAddr(thread->threadId());
+    }
 
     /** Reads this thread's next PC. */
-    virtual MicroPC microPC() override
-    { return cpu->microPC(thread->threadId()); }
+    MicroPC
+    microPC() const override
+    {
+        return cpu->microPC(thread->threadId());
+    }
 
     /** Reads a miscellaneous register. */
-    virtual RegVal readMiscRegNoEffect(int misc_reg) const override
-    { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
+    RegVal
+    readMiscRegNoEffect(RegIndex misc_reg) const override
+    {
+        return cpu->readMiscRegNoEffect(misc_reg, thread->threadId());
+    }
 
     /** Reads a misc. register, including any side-effects the
      * read might have as defined by the architecture. */
-    virtual RegVal readMiscReg(int misc_reg) override
-    { return cpu->readMiscReg(misc_reg, thread->threadId()); }
+    RegVal
+    readMiscReg(RegIndex misc_reg) override
+    {
+        return cpu->readMiscReg(misc_reg, thread->threadId());
+    }
 
     /** Sets a misc. register. */
-    virtual void setMiscRegNoEffect(int misc_reg, RegVal val) override;
+    void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override;
 
     /** Sets a misc. register, including any side-effects the
      * write might have as defined by the architecture. */
-    virtual void setMiscReg(int misc_reg, RegVal val) override;
+    void setMiscReg(RegIndex misc_reg, RegVal val) override;
 
-    virtual RegId flattenRegId(const RegId& regId) const override;
+    RegId flattenRegId(const RegId& regId) const override;
 
     /** Returns the number of consecutive store conditional failures. */
     // @todo: Figure out where these store cond failures should go.
-    virtual unsigned readStCondFailures() override
-    { return thread->storeCondFailures; }
+    unsigned
+    readStCondFailures() const override
+    {
+        return thread->storeCondFailures;
+    }
 
     /** Sets the number of consecutive store conditional failures. */
-    virtual void setStCondFailures(unsigned sc_failures) override
-    { thread->storeCondFailures = sc_failures; }
+    void
+    setStCondFailures(unsigned sc_failures) override
+    {
+        thread->storeCondFailures = sc_failures;
+    }
 
     /** Executes a syscall in SE mode. */
-    virtual void syscall(int64_t callnum, Fault *fault) override
-    { return cpu->syscall(callnum, thread->threadId(), fault); }
+    void
+    syscall(int64_t callnum, Fault *fault) override
+    {
+        return cpu->syscall(callnum, thread->threadId(), fault);
+    }
 
     /** Reads the funcExeInst counter. */
-    virtual Counter readFuncExeInst() override { return thread->funcExeInst; }
+    Counter readFuncExeInst() const override { return thread->funcExeInst; }
 
     /** Returns pointer to the quiesce event. */
-    virtual EndQuiesceEvent *
+    EndQuiesceEvent *
     getQuiesceEvent() override
     {
         return this->thread->quiesceEvent;
@@ -404,46 +453,44 @@ class O3ThreadContext : public ThreadContext
             cpu->squashFromTC(thread->threadId());
     }
 
-    virtual RegVal readIntRegFlat(int idx) override;
-    virtual void setIntRegFlat(int idx, RegVal val) override;
+    RegVal readIntRegFlat(RegIndex idx) const override;
+    void setIntRegFlat(RegIndex idx, RegVal val) override;
 
-    virtual RegVal readFloatRegFlat(int idx) override;
-    virtual void setFloatRegFlat(int idx, RegVal val) override;
+    RegVal readFloatRegFlat(RegIndex idx) const override;
+    void setFloatRegFlat(RegIndex idx, RegVal val) override;
 
-    virtual const VecRegContainer& readVecRegFlat(int idx) const override;
+    const VecRegContainer& readVecRegFlat(RegIndex idx) const override;
     /** Read vector register operand for modification, flat indexing. */
-    virtual VecRegContainer& getWritableVecRegFlat(int idx) override;
-    virtual void setVecRegFlat(int idx, const VecRegContainer& val) override;
+    VecRegContainer& getWritableVecRegFlat(RegIndex idx) override;
+    void setVecRegFlat(RegIndex idx, const VecRegContainer& val) override;
 
     template <typename VecElem>
     VecLaneT<VecElem, true>
-    readVecLaneFlat(int idx, int lId) const
+    readVecLaneFlat(RegIndex idx, int lId) const
     {
         return cpu->template readArchVecLane<VecElem>(idx, lId,
                 thread->threadId());
     }
 
     template <typename LD>
-    void setVecLaneFlat(int idx, int lId, const LD& val)
+    void
+    setVecLaneFlat(int idx, int lId, const LD& val)
     {
         cpu->template setArchVecLane(idx, lId, thread->threadId(), val);
     }
 
-    virtual const VecElem& readVecElemFlat(
-        const RegIndex& idx,
-        const ElemIndex& elemIndex) const override;
-    virtual void setVecElemFlat(
-        const RegIndex& idx,
-        const ElemIndex& elemIdx, const VecElem& val) override;
+    const VecElem &readVecElemFlat(RegIndex idx,
+                                   const ElemIndex& elemIndex) const override;
+    void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx,
+                        const VecElem& val) override;
 
-    virtual const VecPredRegContainer& readVecPredRegFlat(int idx)
-        const override;
-    virtual VecPredRegContainer& getWritableVecPredRegFlat(int idx) override;
-    virtual void setVecPredRegFlat(int idx,
-                                   const VecPredRegContainer& val) override;
+    const VecPredRegContainer& readVecPredRegFlat(RegIndex idx) const override;
+    VecPredRegContainer& getWritableVecPredRegFlat(RegIndex idx) override;
+    void setVecPredRegFlat(RegIndex idx,
+                           const VecPredRegContainer& val) override;
 
-    virtual RegVal readCCRegFlat(int idx) override;
-    virtual void setCCRegFlat(int idx, RegVal val) override;
+    RegVal readCCRegFlat(RegIndex idx) const override;
+    void setCCRegFlat(RegIndex idx, RegVal val) override;
 };
 
 #endif
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index 57e0a45f5..58dee9814 100644
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -205,64 +205,64 @@ O3ThreadContext<Impl>::clearArchRegs()
 
 template <class Impl>
 RegVal
-O3ThreadContext<Impl>::readIntRegFlat(int reg_idx)
+O3ThreadContext<Impl>::readIntRegFlat(RegIndex reg_idx) const
 {
     return cpu->readArchIntReg(reg_idx, thread->threadId());
 }
 
 template <class Impl>
 RegVal
-O3ThreadContext<Impl>::readFloatRegFlat(int reg_idx)
+O3ThreadContext<Impl>::readFloatRegFlat(RegIndex reg_idx) const
 {
     return cpu->readArchFloatReg(reg_idx, thread->threadId());
 }
 
 template <class Impl>
 const TheISA::VecRegContainer&
-O3ThreadContext<Impl>::readVecRegFlat(int reg_id) const
+O3ThreadContext<Impl>::readVecRegFlat(RegIndex reg_id) const
 {
     return cpu->readArchVecReg(reg_id, thread->threadId());
 }
 
 template <class Impl>
 TheISA::VecRegContainer&
-O3ThreadContext<Impl>::getWritableVecRegFlat(int reg_id)
+O3ThreadContext<Impl>::getWritableVecRegFlat(RegIndex reg_id)
 {
     return cpu->getWritableArchVecReg(reg_id, thread->threadId());
 }
 
 template <class Impl>
 const TheISA::VecElem&
-O3ThreadContext<Impl>::readVecElemFlat(const RegIndex& idx,
-                                           const ElemIndex& elemIndex) const
+O3ThreadContext<Impl>::readVecElemFlat(RegIndex idx,
+                                       const ElemIndex& elemIndex) const
 {
     return cpu->readArchVecElem(idx, elemIndex, thread->threadId());
 }
 
 template <class Impl>
 const TheISA::VecPredRegContainer&
-O3ThreadContext<Impl>::readVecPredRegFlat(int reg_id) const
+O3ThreadContext<Impl>::readVecPredRegFlat(RegIndex reg_id) const
 {
     return cpu->readArchVecPredReg(reg_id, thread->threadId());
 }
 
 template <class Impl>
 TheISA::VecPredRegContainer&
-O3ThreadContext<Impl>::getWritableVecPredRegFlat(int reg_id)
+O3ThreadContext<Impl>::getWritableVecPredRegFlat(RegIndex reg_id)
 {
     return cpu->getWritableArchVecPredReg(reg_id, thread->threadId());
 }
 
 template <class Impl>
 RegVal
-O3ThreadContext<Impl>::readCCRegFlat(int reg_idx)
+O3ThreadContext<Impl>::readCCRegFlat(RegIndex reg_idx) const
 {
     return cpu->readArchCCReg(reg_idx, thread->threadId());
 }
 
 template <class Impl>
 void
-O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, RegVal val)
+O3ThreadContext<Impl>::setIntRegFlat(RegIndex reg_idx, RegVal val)
 {
     cpu->setArchIntReg(reg_idx, val, thread->threadId());
 
@@ -271,7 +271,7 @@ O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, RegVal val)
 
 template <class Impl>
 void
-O3ThreadContext<Impl>::setFloatRegFlat(int reg_idx, RegVal val)
+O3ThreadContext<Impl>::setFloatRegFlat(RegIndex reg_idx, RegVal val)
 {
     cpu->setArchFloatReg(reg_idx, val, thread->threadId());
 
@@ -280,7 +280,8 @@ O3ThreadContext<Impl>::setFloatRegFlat(int reg_idx, RegVal val)
 
 template <class Impl>
 void
-O3ThreadContext<Impl>::setVecRegFlat(int reg_idx, const VecRegContainer& val)
+O3ThreadContext<Impl>::setVecRegFlat(
+        RegIndex reg_idx, const VecRegContainer& val)
 {
     cpu->setArchVecReg(reg_idx, val, thread->threadId());
 
@@ -289,7 +290,7 @@ O3ThreadContext<Impl>::setVecRegFlat(int reg_idx, const VecRegContainer& val)
 
 template <class Impl>
 void
-O3ThreadContext<Impl>::setVecElemFlat(const RegIndex& idx,
+O3ThreadContext<Impl>::setVecElemFlat(RegIndex idx,
         const ElemIndex& elemIndex, const VecElem& val)
 {
     cpu->setArchVecElem(idx, elemIndex, val, thread->threadId());
@@ -298,7 +299,7 @@ O3ThreadContext<Impl>::setVecElemFlat(const RegIndex& idx,
 
 template <class Impl>
 void
-O3ThreadContext<Impl>::setVecPredRegFlat(int reg_idx,
+O3ThreadContext<Impl>::setVecPredRegFlat(RegIndex reg_idx,
                                          const VecPredRegContainer& val)
 {
     cpu->setArchVecPredReg(reg_idx, val, thread->threadId());
@@ -308,7 +309,7 @@ O3ThreadContext<Impl>::setVecPredRegFlat(int reg_idx,
 
 template <class Impl>
 void
-O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, RegVal val)
+O3ThreadContext<Impl>::setCCRegFlat(RegIndex reg_idx, RegVal val)
 {
     cpu->setArchCCReg(reg_idx, val, thread->threadId());
 
@@ -342,20 +343,20 @@ O3ThreadContext<Impl>::flattenRegId(const RegId& regId) const
 
 template <class Impl>
 void
-O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val)
+O3ThreadContext<Impl>::setMiscRegNoEffect(RegIndex misc_reg, RegVal val)
 {
     cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
 
     conditionalSquash();
 }
 
-#endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__
 template <class Impl>
 void
-O3ThreadContext<Impl>::setMiscReg(int misc_reg, RegVal val)
+O3ThreadContext<Impl>::setMiscReg(RegIndex misc_reg, RegVal val)
 {
     cpu->setMiscReg(misc_reg, val, thread->threadId());
 
     conditionalSquash();
 }
 
+#endif //__CPU_O3_THREAD_CONTEXT_IMPL_HH__
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index c18bac2ef..7fee8ddc7 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -81,8 +81,7 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
       itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(_isa))
 {
     clearArchRegs();
-    tc = new ProxyThreadContext<SimpleThread>(this);
-    quiesceEvent = new EndQuiesceEvent(tc);
+    quiesceEvent = new EndQuiesceEvent(this);
 }
 
 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
@@ -91,9 +90,7 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
     : ThreadState(_cpu, _thread_num, NULL), isa(_isa), system(_sys), itb(_itb),
       dtb(_dtb), decoder(TheISA::Decoder(_isa))
 {
-    tc = new ProxyThreadContext<SimpleThread>(this);
-
-    quiesceEvent = new EndQuiesceEvent(tc);
+    quiesceEvent = new EndQuiesceEvent(this);
 
     clearArchRegs();
 
@@ -115,15 +112,10 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
         kernelStats = new TheISA::Kernel::Statistics();
 }
 
-SimpleThread::~SimpleThread()
-{
-    delete tc;
-}
-
 void
 SimpleThread::takeOverFrom(ThreadContext *oldContext)
 {
-    ::takeOverFrom(*tc, *oldContext);
+    ::takeOverFrom(*this, *oldContext);
     decoder.takeOverFrom(oldContext->getDecoderPtr());
 
     kernelStats = oldContext->getKernelStats();
@@ -148,7 +140,7 @@ void
 SimpleThread::serialize(CheckpointOut &cp) const
 {
     ThreadState::serialize(cp);
-    ::serialize(*tc, cp);
+    ::serialize(*this, cp);
 }
 
 
@@ -156,20 +148,20 @@ void
 SimpleThread::unserialize(CheckpointIn &cp)
 {
     ThreadState::unserialize(cp);
-    ::unserialize(*tc, cp);
+    ::unserialize(*this, cp);
 }
 
 void
 SimpleThread::startup()
 {
-    isa->startup(tc);
+    isa->startup(this);
 }
 
 void
 SimpleThread::dumpFuncProfile()
 {
     OutputStream *os(simout.create(csprintf("profile.%s.dat", baseCpu->name())));
-    profile->dump(tc, *os->stream());
+    profile->dump(this, *os->stream());
     simout.close(os);
 }
 
@@ -218,7 +210,7 @@ SimpleThread::regStats(const string &name)
 void
 SimpleThread::copyArchRegs(ThreadContext *src_tc)
 {
-    TheISA::copyRegs(src_tc, tc);
+    TheISA::copyRegs(src_tc, this);
 }
 
 // The following methods are defined in src/arch/alpha/ev5.cc for
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 53aa9d7b7..46f142f6f 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -83,9 +83,7 @@ namespace TheISA {
 /**
  * The SimpleThread object provides a combination of the ThreadState
  * object and the ThreadContext interface. It implements the
- * ThreadContext interface so that a ProxyThreadContext class can be
- * made using SimpleThread as the template parameter (see
- * thread_context.hh). It adds to the ThreadState object by adding all
+ * ThreadContext interface and adds to the ThreadState object by adding all
  * the objects needed for simple functional execution, including a
  * simple architectural register file, and pointers to the ITB and DTB
  * in full system mode. For CPU models that do not need more advanced
@@ -96,7 +94,7 @@ namespace TheISA {
  * examples.
  */
 
-class SimpleThread : public ThreadState
+class SimpleThread : public ThreadState, public ThreadContext
 {
   protected:
     typedef TheISA::MachInst MachInst;
@@ -124,11 +122,9 @@ class SimpleThread : public ThreadState
   public:
     std::string name() const
     {
-        return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId());
+        return csprintf("%s.[tid:%i]", baseCpu->name(), threadId());
     }
 
-    ProxyThreadContext<SimpleThread> *tc;
-
     System *system;
 
     BaseTLB *itb;
@@ -146,11 +142,11 @@ class SimpleThread : public ThreadState
                  Process *_process, BaseTLB *_itb, BaseTLB *_dtb,
                  TheISA::ISA *_isa);
 
-    virtual ~SimpleThread();
+    virtual ~SimpleThread() {}
 
-    virtual void takeOverFrom(ThreadContext *oldContext);
+    void takeOverFrom(ThreadContext *oldContext) override;
 
-    void regStats(const std::string &name);
+    void regStats(const std::string &name) override;
 
     void copyState(ThreadContext *oldContext);
 
@@ -167,7 +163,7 @@ class SimpleThread : public ThreadState
      *  when a ThreadContext must be passed to objects outside of the
      *  CPU.
      */
-    ThreadContext *getTC() { return tc; }
+    ThreadContext *getTC() { return this; }
 
     void demapPage(Addr vaddr, uint64_t asn)
     {
@@ -185,7 +181,7 @@ class SimpleThread : public ThreadState
         dtb->demapPage(vaddr, asn);
     }
 
-    void dumpFuncProfile();
+    void dumpFuncProfile() override;
 
     Fault hwrei();
 
@@ -195,36 +191,86 @@ class SimpleThread : public ThreadState
      * ThreadContext interface functions.
      ******************************************/
 
-    BaseCPU *getCpuPtr() { return baseCpu; }
+    BaseCPU *getCpuPtr() override { return baseCpu; }
+
+    int cpuId() const override { return ThreadState::cpuId(); }
+    uint32_t socketId() const override { return ThreadState::socketId(); }
+    int threadId() const override { return ThreadState::threadId(); }
+    void setThreadId(int id) override { ThreadState::setThreadId(id); }
+    ContextID contextId() const override { return ThreadState::contextId(); }
+    void setContextId(ContextID id) override { ThreadState::setContextId(id); }
+
+    BaseTLB *getITBPtr() override { return itb; }
 
-    BaseTLB *getITBPtr() { return itb; }
+    BaseTLB *getDTBPtr() override { return dtb; }
 
-    BaseTLB *getDTBPtr() { return dtb; }
+    CheckerCPU *getCheckerCpuPtr() override { return NULL; }
 
-    CheckerCPU *getCheckerCpuPtr() { return NULL; }
+    TheISA::ISA *getIsaPtr() override { return isa; }
 
-    TheISA::ISA *getIsaPtr() { return isa; }
+    TheISA::Decoder *getDecoderPtr() override { return &decoder; }
 
-    TheISA::Decoder *getDecoderPtr() { return &decoder; }
+    System *getSystemPtr() override { return system; }
+
+    TheISA::Kernel::Statistics *
+    getKernelStats()
+    {
+        return ThreadState::getKernelStats();
+    }
 
-    System *getSystemPtr() { return system; }
+    PortProxy &getPhysProxy() { return ThreadState::getPhysProxy(); }
+    FSTranslatingPortProxy &
+    getVirtProxy()
+    {
+        return ThreadState::getVirtProxy();
+    }
 
-    Status status() const { return _status; }
+    void initMemProxies(ThreadContext *tc) { ThreadState::initMemProxies(tc); }
+    SETranslatingPortProxy &
+    getMemProxy()
+    {
+        return ThreadState::getMemProxy();
+    }
 
-    void setStatus(Status newStatus) { _status = newStatus; }
+    Process *getProcessPtr() { return ThreadState::getProcessPtr(); }
+    void setProcessPtr(Process *p) override { ThreadState::setProcessPtr(p); }
+
+    Status status() const override { return _status; }
+
+    void setStatus(Status newStatus) override { _status = newStatus; }
 
     /// Set the status to Active.
-    void activate();
+    void activate() override;
 
     /// Set the status to Suspended.
-    void suspend();
+    void suspend() override;
 
     /// Set the status to Halted.
-    void halt();
+    void halt() override;
 
-    void copyArchRegs(ThreadContext *tc);
+    EndQuiesceEvent *
+    getQuiesceEvent() override
+    {
+        return ThreadState::getQuiesceEvent();
+    }
 
-    void clearArchRegs()
+    Tick
+    readLastActivate() override
+    {
+        return ThreadState::readLastActivate();
+    }
+    Tick
+    readLastSuspend() override
+    {
+        return ThreadState::readLastSuspend();
+    }
+
+    void profileClear() override { ThreadState::profileClear(); }
+    void profileSample() override { ThreadState::profileSample(); }
+
+    void copyArchRegs(ThreadContext *tc) override;
+
+    void clearArchRegs() override
     {
         _pcState = 0;
         memset(intRegs, 0, sizeof(intRegs));
@@ -245,7 +291,7 @@ class SimpleThread : public ThreadState
     // New accessors for new decoder.
     //
     RegVal
-    readIntReg(int reg_idx)
+    readIntReg(RegIndex reg_idx) const override
     {
         int flatIndex = isa->flattenIntIndex(reg_idx);
         assert(flatIndex < TheISA::NumIntRegs);
@@ -256,7 +302,7 @@ class SimpleThread : public ThreadState
     }
 
     RegVal
-    readFloatReg(int reg_idx)
+    readFloatReg(RegIndex reg_idx) const override
     {
         int flatIndex = isa->flattenFloatIndex(reg_idx);
         assert(flatIndex < TheISA::NumFloatRegs);
@@ -267,7 +313,7 @@ class SimpleThread : public ThreadState
     }
 
     const VecRegContainer&
-    readVecReg(const RegId& reg) const
+    readVecReg(const RegId& reg) const override
     {
         int flatIndex = isa->flattenVecIndex(reg.index());
         assert(flatIndex < TheISA::NumVecRegs);
@@ -278,7 +324,7 @@ class SimpleThread : public ThreadState
     }
 
     VecRegContainer&
-    getWritableVecReg(const RegId& reg)
+    getWritableVecReg(const RegId& reg) override
     {
         int flatIndex = isa->flattenVecIndex(reg.index());
         assert(flatIndex < TheISA::NumVecRegs);
@@ -305,27 +351,36 @@ class SimpleThread : public ThreadState
 
     /** Reads source vector 8bit operand. */
     virtual ConstVecLane8
-    readVec8BitLaneReg(const RegId& reg) const
-    { return readVecLane<uint8_t>(reg); }
+    readVec8BitLaneReg(const RegId &reg) const override
+    {
+        return readVecLane<uint8_t>(reg);
+    }
 
     /** Reads source vector 16bit operand. */
     virtual ConstVecLane16
-    readVec16BitLaneReg(const RegId& reg) const
-    { return readVecLane<uint16_t>(reg); }
+    readVec16BitLaneReg(const RegId &reg) const override
+    {
+        return readVecLane<uint16_t>(reg);
+    }
 
     /** Reads source vector 32bit operand. */
     virtual ConstVecLane32
-    readVec32BitLaneReg(const RegId& reg) const
-    { return readVecLane<uint32_t>(reg); }
+    readVec32BitLaneReg(const RegId &reg) const override
+    {
+        return readVecLane<uint32_t>(reg);
+    }
 
     /** Reads source vector 64bit operand. */
     virtual ConstVecLane64
-    readVec64BitLaneReg(const RegId& reg) const
-    { return readVecLane<uint64_t>(reg); }
+    readVec64BitLaneReg(const RegId &reg) const override
+    {
+        return readVecLane<uint64_t>(reg);
+    }
 
     /** Write a lane of the destination vector register. */
     template <typename LD>
-    void setVecLaneT(const RegId& reg, const LD& val)
+    void
+    setVecLaneT(const RegId &reg, const LD &val)
     {
         int flatIndex = isa->flattenVecIndex(reg.index());
         assert(flatIndex < TheISA::NumVecRegs);
@@ -333,21 +388,33 @@ class SimpleThread : public ThreadState
         DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] to %lx.\n",
                 reg.index(), flatIndex, reg.elemIndex(), val);
     }
-    virtual void setVecLane(const RegId& reg,
-            const LaneData<LaneSize::Byte>& val)
-    { return setVecLaneT(reg, val); }
-    virtual void setVecLane(const RegId& reg,
-            const LaneData<LaneSize::TwoByte>& val)
-    { return setVecLaneT(reg, val); }
-    virtual void setVecLane(const RegId& reg,
-            const LaneData<LaneSize::FourByte>& val)
-    { return setVecLaneT(reg, val); }
-    virtual void setVecLane(const RegId& reg,
-            const LaneData<LaneSize::EightByte>& val)
-    { return setVecLaneT(reg, val); }
+    virtual void
+    setVecLane(const RegId &reg, const LaneData<LaneSize::Byte> &val) override
+    {
+        return setVecLaneT(reg, val);
+    }
+    virtual void
+    setVecLane(const RegId &reg,
+               const LaneData<LaneSize::TwoByte> &val) override
+    {
+        return setVecLaneT(reg, val);
+    }
+    virtual void
+    setVecLane(const RegId &reg,
+               const LaneData<LaneSize::FourByte> &val) override
+    {
+        return setVecLaneT(reg, val);
+    }
+    virtual void
+    setVecLane(const RegId &reg,
+               const LaneData<LaneSize::EightByte> &val) override
+    {
+        return setVecLaneT(reg, val);
+    }
     /** @} */
 
-    const VecElem& readVecElem(const RegId& reg) const
+    const VecElem &
+    readVecElem(const RegId &reg) const override
     {
         int flatIndex = isa->flattenVecElemIndex(reg.index());
         assert(flatIndex < TheISA::NumVecRegs);
@@ -357,8 +424,8 @@ class SimpleThread : public ThreadState
         return regVal;
     }
 
-    const VecPredRegContainer&
-    readVecPredReg(const RegId& reg) const
+    const VecPredRegContainer &
+    readVecPredReg(const RegId &reg) const override
     {
         int flatIndex = isa->flattenVecPredIndex(reg.index());
         assert(flatIndex < TheISA::NumVecPredRegs);
@@ -368,8 +435,8 @@ class SimpleThread : public ThreadState
         return regVal;
     }
 
-    VecPredRegContainer&
-    getWritableVecPredReg(const RegId& reg)
+    VecPredRegContainer &
+    getWritableVecPredReg(const RegId &reg) override
     {
         int flatIndex = isa->flattenVecPredIndex(reg.index());
         assert(flatIndex < TheISA::NumVecPredRegs);
@@ -381,7 +448,7 @@ class SimpleThread : public ThreadState
     }
 
     RegVal
-    readCCReg(int reg_idx)
+    readCCReg(RegIndex reg_idx) const override
     {
 #ifdef ISA_HAS_CC_REGS
         int flatIndex = isa->flattenCCIndex(reg_idx);
@@ -398,7 +465,7 @@ class SimpleThread : public ThreadState
     }
 
     void
-    setIntReg(int reg_idx, RegVal val)
+    setIntReg(RegIndex reg_idx, RegVal val) override
     {
         int flatIndex = isa->flattenIntIndex(reg_idx);
         assert(flatIndex < TheISA::NumIntRegs);
@@ -408,7 +475,7 @@ class SimpleThread : public ThreadState
     }
 
     void
-    setFloatReg(int reg_idx, RegVal val)
+    setFloatReg(RegIndex reg_idx, RegVal val) override
     {
         int flatIndex = isa->flattenFloatIndex(reg_idx);
         assert(flatIndex < TheISA::NumFloatRegs);
@@ -421,7 +488,7 @@ class SimpleThread : public ThreadState
     }
 
     void
-    setVecReg(const RegId& reg, const VecRegContainer& val)
+    setVecReg(const RegId &reg, const VecRegContainer &val) override
     {
         int flatIndex = isa->flattenVecIndex(reg.index());
         assert(flatIndex < TheISA::NumVecRegs);
@@ -431,7 +498,7 @@ class SimpleThread : public ThreadState
     }
 
     void
-    setVecElem(const RegId& reg, const VecElem& val)
+    setVecElem(const RegId &reg, const VecElem &val) override
     {
         int flatIndex = isa->flattenVecElemIndex(reg.index());
         assert(flatIndex < TheISA::NumVecRegs);
@@ -441,7 +508,7 @@ class SimpleThread : public ThreadState
     }
 
     void
-    setVecPredReg(const RegId& reg, const VecPredRegContainer& val)
+    setVecPredReg(const RegId &reg, const VecPredRegContainer &val) override
     {
         int flatIndex = isa->flattenVecPredIndex(reg.index());
         assert(flatIndex < TheISA::NumVecPredRegs);
@@ -451,7 +518,7 @@ class SimpleThread : public ThreadState
     }
 
     void
-    setCCReg(int reg_idx, RegVal val)
+    setCCReg(RegIndex reg_idx, RegVal val) override
     {
 #ifdef ISA_HAS_CC_REGS
         int flatIndex = isa->flattenCCIndex(reg_idx);
@@ -464,174 +531,167 @@ class SimpleThread : public ThreadState
 #endif
     }
 
-    TheISA::PCState
-    pcState()
-    {
-        return _pcState;
-    }
+    TheISA::PCState pcState() const override { return _pcState; }
+    void pcState(const TheISA::PCState &val) override { _pcState = val; }
 
     void
-    pcState(const TheISA::PCState &val)
+    pcStateNoRecord(const TheISA::PCState &val) override
     {
         _pcState = val;
     }
 
-    void
-    pcStateNoRecord(const TheISA::PCState &val)
-    {
-        _pcState = val;
-    }
+    Addr instAddr() const override  { return _pcState.instAddr(); }
+    Addr nextInstAddr() const override { return _pcState.nextInstAddr(); }
+    MicroPC microPC() const override { return _pcState.microPC(); }
+    bool readPredicate() const { return predicate; }
+    void setPredicate(bool val) { predicate = val; }
 
-    Addr
-    instAddr()
+    RegVal
+    readMiscRegNoEffect(RegIndex misc_reg) const override
     {
-        return _pcState.instAddr();
+        return isa->readMiscRegNoEffect(misc_reg);
     }
 
-    Addr
-    nextInstAddr()
+    RegVal
+    readMiscReg(RegIndex misc_reg) override
     {
-        return _pcState.nextInstAddr();
+        return isa->readMiscReg(misc_reg, this);
     }
 
     void
-    setNPC(Addr val)
+    setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
     {
-        _pcState.setNPC(val);
+        return isa->setMiscRegNoEffect(misc_reg, val);
     }
 
-    MicroPC
-    microPC()
+    void
+    setMiscReg(RegIndex misc_reg, RegVal val) override
     {
-        return _pcState.microPC();
+        return isa->setMiscReg(misc_reg, val, this);
     }
 
-    bool readPredicate()
+    RegId
+    flattenRegId(const RegId& regId) const override
     {
-        return predicate;
+        return isa->flattenRegId(regId);
     }
 
-    void setPredicate(bool val)
-    {
-        predicate = val;
-    }
+    unsigned readStCondFailures() const override { return storeCondFailures; }
 
-    RegVal
-    readMiscRegNoEffect(int misc_reg, ThreadID tid=0) const
+    void
+    setStCondFailures(unsigned sc_failures) override
     {
-        return isa->readMiscRegNoEffect(misc_reg);
+        storeCondFailures = sc_failures;
     }
 
-    RegVal
-    readMiscReg(int misc_reg, ThreadID tid=0)
+    Counter
+    readFuncExeInst() const override
     {
-        return isa->readMiscReg(misc_reg, tc);
+        return ThreadState::readFuncExeInst();
     }
 
     void
-    setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid = 0)
+    syscall(int64_t callnum, Fault *fault) override
     {
-        return isa->setMiscRegNoEffect(misc_reg, val);
+        process->syscall(callnum, this, fault);
     }
 
+    RegVal readIntRegFlat(RegIndex idx) const override { return intRegs[idx]; }
     void
-    setMiscReg(int misc_reg, RegVal val, ThreadID tid = 0)
+    setIntRegFlat(RegIndex idx, RegVal val) override
     {
-        return isa->setMiscReg(misc_reg, val, tc);
+        intRegs[idx] = val;
     }
 
-    RegId
-    flattenRegId(const RegId& regId) const
+    RegVal
+    readFloatRegFlat(RegIndex idx) const override
     {
-        return isa->flattenRegId(regId);
+        return floatRegs[idx];
     }
-
-    unsigned readStCondFailures() { return storeCondFailures; }
-
-    void setStCondFailures(unsigned sc_failures)
-    { storeCondFailures = sc_failures; }
-
     void
-    syscall(int64_t callnum, Fault *fault)
+    setFloatRegFlat(RegIndex idx, RegVal val) override
     {
-        process->syscall(callnum, tc, fault);
+        floatRegs[idx] = val;
     }
 
-    RegVal readIntRegFlat(int idx) { return intRegs[idx]; }
-    void setIntRegFlat(int idx, RegVal val) { intRegs[idx] = val; }
-
-    RegVal readFloatRegFlat(int idx) { return floatRegs[idx]; }
-    void setFloatRegFlat(int idx, RegVal val) { floatRegs[idx] = val; }
-
     const VecRegContainer &
-    readVecRegFlat(const RegIndex& reg) const
+    readVecRegFlat(RegIndex reg) const override
     {
         return vecRegs[reg];
     }
 
     VecRegContainer &
-    getWritableVecRegFlat(const RegIndex& reg)
+    getWritableVecRegFlat(RegIndex reg) override
     {
         return vecRegs[reg];
     }
 
     void
-    setVecRegFlat(const RegIndex& reg, const VecRegContainer& val)
+    setVecRegFlat(RegIndex reg, const VecRegContainer &val) override
     {
         vecRegs[reg] = val;
     }
 
     template <typename T>
     VecLaneT<T, true>
-    readVecLaneFlat(const RegIndex& reg, int lId) const
+    readVecLaneFlat(RegIndex reg, int lId) const
     {
         return vecRegs[reg].laneView<T>(lId);
     }
 
     template <typename LD>
     void
-    setVecLaneFlat(const RegIndex& reg, int lId, const LD& val)
+    setVecLaneFlat(RegIndex reg, int lId, const LD &val)
     {
         vecRegs[reg].laneView<typename LD::UnderlyingType>(lId) = val;
     }
 
     const VecElem &
-    readVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex) const
+    readVecElemFlat(RegIndex reg, const ElemIndex &elemIndex) const override
     {
         return vecRegs[reg].as<TheISA::VecElem>()[elemIndex];
     }
 
     void
-    setVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex,
-                   const VecElem val)
+    setVecElemFlat(RegIndex reg, const ElemIndex &elemIndex,
+                   const VecElem &val) override
     {
         vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val;
     }
 
-    const VecPredRegContainer& readVecPredRegFlat(const RegIndex& reg) const
+    const VecPredRegContainer &
+    readVecPredRegFlat(RegIndex reg) const override
     {
         return vecPredRegs[reg];
     }
 
-    VecPredRegContainer& getWritableVecPredRegFlat(const RegIndex& reg)
+    VecPredRegContainer &
+    getWritableVecPredRegFlat(RegIndex reg) override
     {
         return vecPredRegs[reg];
     }
 
-    void setVecPredRegFlat(const RegIndex& reg, const VecPredRegContainer& val)
+    void
+    setVecPredRegFlat(RegIndex reg, const VecPredRegContainer &val) override
     {
         vecPredRegs[reg] = val;
     }
 
 #ifdef ISA_HAS_CC_REGS
-    RegVal readCCRegFlat(int idx) { return ccRegs[idx]; }
-    void setCCRegFlat(int idx, RegVal val) { ccRegs[idx] = val; }
+    RegVal readCCRegFlat(RegIndex idx) const override { return ccRegs[idx]; }
+    void setCCRegFlat(RegIndex idx, RegVal val) override { ccRegs[idx] = val; }
 #else
-    RegVal readCCRegFlat(int idx)
-    { panic("readCCRegFlat w/no CC regs!\n"); }
+    RegVal
+    readCCRegFlat(RegIndex idx) const override
+    {
+        panic("readCCRegFlat w/no CC regs!\n");
+    }
 
-    void setCCRegFlat(int idx, RegVal val)
-    { panic("setCCRegFlat w/no CC regs!\n"); }
+    void
+    setCCRegFlat(RegIndex idx, RegVal val) override
+    {
+        panic("setCCRegFlat w/no CC regs!\n");
+    }
 #endif
 };
 
diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index d122dd612..35d96a4e7 100644
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -163,7 +163,7 @@ ThreadContext::quiesceTick(Tick resume)
 }
 
 void
-serialize(ThreadContext &tc, CheckpointOut &cp)
+serialize(const ThreadContext &tc, CheckpointOut &cp)
 {
     using namespace TheISA;
 
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 2a991f68f..09f2a1eab 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -81,8 +81,8 @@ namespace TheISA {
  * anything outside of the CPU. It provides all accessor methods to
  * state that might be needed by external objects, ranging from
  * register values to things such as kernel stats. It is an abstract
- * base class; the CPU can create its own ThreadContext by either
- * deriving from it, or using the templated ProxyThreadContext.
+ * base class; the CPU can create its own ThreadContext by
+ * deriving from it.
  *
  * The ThreadContext is slightly different than the ExecContext.  The
  * ThreadContext provides access to an individual thread's state; an
@@ -134,9 +134,9 @@ class ThreadContext
 
     virtual void setThreadId(int id) = 0;
 
-    virtual int contextId() const = 0;
+    virtual ContextID contextId() const = 0;
 
-    virtual void setContextId(int id) = 0;
+    virtual void setContextId(ContextID id) = 0;
 
     virtual BaseTLB *getITBPtr() = 0;
 
@@ -212,9 +212,9 @@ class ThreadContext
     //
     // New accessors for new decoder.
     //
-    virtual RegVal readIntReg(int reg_idx) = 0;
+    virtual RegVal readIntReg(RegIndex reg_idx) const = 0;
 
-    virtual RegVal readFloatReg(int reg_idx) = 0;
+    virtual RegVal readFloatReg(RegIndex reg_idx) const = 0;
 
     virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0;
     virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0;
@@ -254,11 +254,11 @@ class ThreadContext
         const = 0;
     virtual VecPredRegContainer& getWritableVecPredReg(const RegId& reg) = 0;
 
-    virtual RegVal readCCReg(int reg_idx) = 0;
+    virtual RegVal readCCReg(RegIndex reg_idx) const = 0;
 
-    virtual void setIntReg(int reg_idx, RegVal val) = 0;
+    virtual void setIntReg(RegIndex reg_idx, RegVal val) = 0;
 
-    virtual void setFloatReg(int reg_idx, RegVal val) = 0;
+    virtual void setFloatReg(RegIndex reg_idx, RegVal val) = 0;
 
     virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0;
 
@@ -267,9 +267,9 @@ class ThreadContext
     virtual void setVecPredReg(const RegId& reg,
                                const VecPredRegContainer& val) = 0;
 
-    virtual void setCCReg(int reg_idx, RegVal val) = 0;
+    virtual void setCCReg(RegIndex reg_idx, RegVal val) = 0;
 
-    virtual TheISA::PCState pcState() = 0;
+    virtual TheISA::PCState pcState() const = 0;
 
     virtual void pcState(const TheISA::PCState &val) = 0;
 
@@ -283,19 +283,19 @@ class ThreadContext
 
     virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
 
-    virtual Addr instAddr() = 0;
+    virtual Addr instAddr() const = 0;
 
-    virtual Addr nextInstAddr() = 0;
+    virtual Addr nextInstAddr() const = 0;
 
-    virtual MicroPC microPC() = 0;
+    virtual MicroPC microPC() const = 0;
 
-    virtual RegVal readMiscRegNoEffect(int misc_reg) const = 0;
+    virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const = 0;
 
-    virtual RegVal readMiscReg(int misc_reg) = 0;
+    virtual RegVal readMiscReg(RegIndex misc_reg) = 0;
 
-    virtual void setMiscRegNoEffect(int misc_reg, RegVal val) = 0;
+    virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) = 0;
 
-    virtual void setMiscReg(int misc_reg, RegVal val) = 0;
+    virtual void setMiscReg(RegIndex misc_reg, RegVal val) = 0;
 
     virtual RegId flattenRegId(const RegId& regId) const = 0;
 
@@ -312,12 +312,12 @@ class ThreadContext
 
     // Also not necessarily the best location for these two.  Hopefully will go
     // away once we decide upon where st cond failures goes.
-    virtual unsigned readStCondFailures() = 0;
+    virtual unsigned readStCondFailures() const = 0;
 
     virtual void setStCondFailures(unsigned sc_failures) = 0;
 
     // Same with st cond failures.
-    virtual Counter readFuncExeInst() = 0;
+    virtual Counter readFuncExeInst() const = 0;
 
     virtual void syscall(int64_t callnum, Fault *fault) = 0;
 
@@ -341,302 +341,33 @@ class ThreadContext
      * serialization code to access all registers.
      */
 
-    virtual RegVal readIntRegFlat(int idx) = 0;
-    virtual void setIntRegFlat(int idx, RegVal val) = 0;
+    virtual RegVal readIntRegFlat(RegIndex idx) const = 0;
+    virtual void setIntRegFlat(RegIndex idx, RegVal val) = 0;
 
-    virtual RegVal readFloatRegFlat(int idx) = 0;
-    virtual void setFloatRegFlat(int idx, RegVal val) = 0;
+    virtual RegVal readFloatRegFlat(RegIndex idx) const = 0;
+    virtual void setFloatRegFlat(RegIndex idx, RegVal val) = 0;
 
-    virtual const VecRegContainer& readVecRegFlat(int idx) const = 0;
-    virtual VecRegContainer& getWritableVecRegFlat(int idx) = 0;
-    virtual void setVecRegFlat(int idx, const VecRegContainer& val) = 0;
+    virtual const VecRegContainer& readVecRegFlat(RegIndex idx) const = 0;
+    virtual VecRegContainer& getWritableVecRegFlat(RegIndex idx) = 0;
+    virtual void setVecRegFlat(RegIndex idx, const VecRegContainer& val) = 0;
 
-    virtual const VecElem& readVecElemFlat(const RegIndex& idx,
+    virtual const VecElem& readVecElemFlat(RegIndex idx,
                                            const ElemIndex& elemIdx) const = 0;
-    virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex& elemIdx,
+    virtual void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx,
                                 const VecElem& val) = 0;
 
-    virtual const VecPredRegContainer& readVecPredRegFlat(int idx) const = 0;
-    virtual VecPredRegContainer& getWritableVecPredRegFlat(int idx) = 0;
-    virtual void setVecPredRegFlat(int idx,
+    virtual const VecPredRegContainer &
+        readVecPredRegFlat(RegIndex idx) const = 0;
+    virtual VecPredRegContainer& getWritableVecPredRegFlat(RegIndex idx) = 0;
+    virtual void setVecPredRegFlat(RegIndex idx,
                                    const VecPredRegContainer& val) = 0;
 
-    virtual RegVal readCCRegFlat(int idx) = 0;
-    virtual void setCCRegFlat(int idx, RegVal val) = 0;
+    virtual RegVal readCCRegFlat(RegIndex idx) const = 0;
+    virtual void setCCRegFlat(RegIndex idx, RegVal val) = 0;
     /** @} */
 
 };
 
-/**
- * ProxyThreadContext class that provides a way to implement a
- * ThreadContext without having to derive from it. ThreadContext is an
- * abstract class, so anything that derives from it and uses its
- * interface will pay the overhead of virtual function calls.  This
- * class is created to enable a user-defined Thread object to be used
- * wherever ThreadContexts are used, without paying the overhead of
- * virtual function calls when it is used by itself.  See
- * simple_thread.hh for an example of this.
- */
-template <class TC>
-class ProxyThreadContext : public ThreadContext
-{
-  public:
-    ProxyThreadContext(TC *actual_tc)
-    { actualTC = actual_tc; }
-
-  private:
-    TC *actualTC;
-
-  public:
-
-    BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
-
-    int cpuId() const { return actualTC->cpuId(); }
-
-    uint32_t socketId() const { return actualTC->socketId(); }
-
-    int threadId() const { return actualTC->threadId(); }
-
-    void setThreadId(int id) { actualTC->setThreadId(id); }
-
-    int contextId() const { return actualTC->contextId(); }
-
-    void setContextId(int id) { actualTC->setContextId(id); }
-
-    BaseTLB *getITBPtr() { return actualTC->getITBPtr(); }
-
-    BaseTLB *getDTBPtr() { return actualTC->getDTBPtr(); }
-
-    CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }
-
-    TheISA::ISA *getIsaPtr() { return actualTC->getIsaPtr(); }
-
-    TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
-
-    System *getSystemPtr() { return actualTC->getSystemPtr(); }
-
-    TheISA::Kernel::Statistics *getKernelStats()
-    { return actualTC->getKernelStats(); }
-
-    PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
-
-    FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); }
-
-    void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); }
-
-    SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
-
-    Process *getProcessPtr() { return actualTC->getProcessPtr(); }
-
-    void setProcessPtr(Process *p) { actualTC->setProcessPtr(p); }
-
-    Status status() const { return actualTC->status(); }
-
-    void setStatus(Status new_status) { actualTC->setStatus(new_status); }
-
-    /// Set the status to Active.
-    void activate() { actualTC->activate(); }
-
-    /// Set the status to Suspended.
-    void suspend() { actualTC->suspend(); }
-
-    /// Set the status to Halted.
-    void halt() { actualTC->halt(); }
-
-    /// Quiesce thread context
-    void quiesce() { actualTC->quiesce(); }
-
-    /// Quiesce, suspend, and schedule activate at resume
-    void quiesceTick(Tick resume) { actualTC->quiesceTick(resume); }
-
-    void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
-
-    void takeOverFrom(ThreadContext *oldContext)
-    { actualTC->takeOverFrom(oldContext); }
-
-    void regStats(const std::string &name) { actualTC->regStats(name); }
-
-    EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
-
-    Tick readLastActivate() { return actualTC->readLastActivate(); }
-    Tick readLastSuspend() { return actualTC->readLastSuspend(); }
-
-    void profileClear() { return actualTC->profileClear(); }
-    void profileSample() { return actualTC->profileSample(); }
-
-    // @todo: Do I need this?
-    void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
-
-    void clearArchRegs() { actualTC->clearArchRegs(); }
-
-    //
-    // New accessors for new decoder.
-    //
-    RegVal readIntReg(int reg_idx)
-    { return actualTC->readIntReg(reg_idx); }
-
-    RegVal readFloatReg(int reg_idx)
-    { return actualTC->readFloatReg(reg_idx); }
-
-    const VecRegContainer& readVecReg(const RegId& reg) const
-    { return actualTC->readVecReg(reg); }
-
-    VecRegContainer& getWritableVecReg(const RegId& reg)
-    { return actualTC->getWritableVecReg(reg); }
-
-    /** Vector Register Lane Interfaces. */
-    /** @{ */
-    /** Reads source vector 8bit operand. */
-    ConstVecLane8
-    readVec8BitLaneReg(const RegId& reg) const
-    { return actualTC->readVec8BitLaneReg(reg); }
-
-    /** Reads source vector 16bit operand. */
-    ConstVecLane16
-    readVec16BitLaneReg(const RegId& reg) const
-    { return actualTC->readVec16BitLaneReg(reg); }
-
-    /** Reads source vector 32bit operand. */
-    ConstVecLane32
-    readVec32BitLaneReg(const RegId& reg) const
-    { return actualTC->readVec32BitLaneReg(reg); }
-
-    /** Reads source vector 64bit operand. */
-    ConstVecLane64
-    readVec64BitLaneReg(const RegId& reg) const
-    { return actualTC->readVec64BitLaneReg(reg); }
-
-    /** Write a lane of the destination vector register. */
-    virtual void setVecLane(const RegId& reg,
-            const LaneData<LaneSize::Byte>& val)
-    { return actualTC->setVecLane(reg, val); }
-    virtual void setVecLane(const RegId& reg,
-            const LaneData<LaneSize::TwoByte>& val)
-    { return actualTC->setVecLane(reg, val); }
-    virtual void setVecLane(const RegId& reg,
-            const LaneData<LaneSize::FourByte>& val)
-    { return actualTC->setVecLane(reg, val); }
-    virtual void setVecLane(const RegId& reg,
-            const LaneData<LaneSize::EightByte>& val)
-    { return actualTC->setVecLane(reg, val); }
-    /** @} */
-
-    const VecElem& readVecElem(const RegId& reg) const
-    { return actualTC->readVecElem(reg); }
-
-    const VecPredRegContainer& readVecPredReg(const RegId& reg) const
-    { return actualTC->readVecPredReg(reg); }
-
-    VecPredRegContainer& getWritableVecPredReg(const RegId& reg)
-    { return actualTC->getWritableVecPredReg(reg); }
-
-    RegVal readCCReg(int reg_idx)
-    { return actualTC->readCCReg(reg_idx); }
-
-    void setIntReg(int reg_idx, RegVal val)
-    { actualTC->setIntReg(reg_idx, val); }
-
-    void setFloatReg(int reg_idx, RegVal val)
-    { actualTC->setFloatReg(reg_idx, val); }
-
-    void setVecReg(const RegId& reg, const VecRegContainer& val)
-    { actualTC->setVecReg(reg, val); }
-
-    void setVecPredReg(const RegId& reg, const VecPredRegContainer& val)
-    { actualTC->setVecPredReg(reg, val); }
-
-    void setVecElem(const RegId& reg, const VecElem& val)
-    { actualTC->setVecElem(reg, val); }
-
-    void setCCReg(int reg_idx, RegVal val)
-    { actualTC->setCCReg(reg_idx, val); }
-
-    TheISA::PCState pcState() { return actualTC->pcState(); }
-
-    void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
-
-    void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
-
-    Addr instAddr() { return actualTC->instAddr(); }
-    Addr nextInstAddr() { return actualTC->nextInstAddr(); }
-    MicroPC microPC() { return actualTC->microPC(); }
-
-    bool readPredicate() { return actualTC->readPredicate(); }
-
-    void setPredicate(bool val)
-    { actualTC->setPredicate(val); }
-
-    RegVal readMiscRegNoEffect(int misc_reg) const
-    { return actualTC->readMiscRegNoEffect(misc_reg); }
-
-    RegVal readMiscReg(int misc_reg)
-    { return actualTC->readMiscReg(misc_reg); }
-
-    void setMiscRegNoEffect(int misc_reg, RegVal val)
-    { return actualTC->setMiscRegNoEffect(misc_reg, val); }
-
-    void setMiscReg(int misc_reg, RegVal val)
-    { return actualTC->setMiscReg(misc_reg, val); }
-
-    RegId flattenRegId(const RegId& regId) const
-    { return actualTC->flattenRegId(regId); }
-
-    unsigned readStCondFailures()
-    { return actualTC->readStCondFailures(); }
-
-    void setStCondFailures(unsigned sc_failures)
-    { actualTC->setStCondFailures(sc_failures); }
-
-    void syscall(int64_t callnum, Fault *fault)
-    { actualTC->syscall(callnum, fault); }
-
-    Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
-
-    RegVal readIntRegFlat(int idx)
-    { return actualTC->readIntRegFlat(idx); }
-
-    void setIntRegFlat(int idx, RegVal val)
-    { actualTC->setIntRegFlat(idx, val); }
-
-    RegVal readFloatRegFlat(int idx)
-    { return actualTC->readFloatRegFlat(idx); }
-
-    void setFloatRegFlat(int idx, RegVal val)
-    { actualTC->setFloatRegFlat(idx, val); }
-
-    const VecRegContainer& readVecRegFlat(int id) const
-    { return actualTC->readVecRegFlat(id); }
-
-    VecRegContainer& getWritableVecRegFlat(int id)
-    { return actualTC->getWritableVecRegFlat(id); }
-
-    void setVecRegFlat(int idx, const VecRegContainer& val)
-    { actualTC->setVecRegFlat(idx, val); }
-
-    const VecElem& readVecElemFlat(const RegIndex& id,
-                                   const ElemIndex& elemIndex) const
-    { return actualTC->readVecElemFlat(id, elemIndex); }
-
-    void setVecElemFlat(const RegIndex& id, const ElemIndex& elemIndex,
-                        const VecElem& val)
-    { actualTC->setVecElemFlat(id, elemIndex, val); }
-
-    const VecPredRegContainer& readVecPredRegFlat(int id) const
-    { return actualTC->readVecPredRegFlat(id); }
-
-    VecPredRegContainer& getWritableVecPredRegFlat(int id)
-    { return actualTC->getWritableVecPredRegFlat(id); }
-
-    void setVecPredRegFlat(int idx, const VecPredRegContainer& val)
-    { actualTC->setVecPredRegFlat(idx, val); }
-
-    RegVal readCCRegFlat(int idx)
-    { return actualTC->readCCRegFlat(idx); }
-
-    void setCCRegFlat(int idx, RegVal val)
-    { actualTC->setCCRegFlat(idx, val); }
-};
-
 /** @{ */
 /**
  * Thread context serialization helpers
@@ -647,7 +378,7 @@ class ProxyThreadContext : public ThreadContext
  * be confusing when the ThreadContext is exported via a proxy.
  */
 
-void serialize(ThreadContext &tc, CheckpointOut &cp);
+void serialize(const ThreadContext &tc, CheckpointOut &cp);
 void unserialize(ThreadContext &tc, CheckpointIn &cp);
 
 /** @} */
diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh
index 5cbc3322b..e3b6af9da 100644
--- a/src/cpu/thread_state.hh
+++ b/src/cpu/thread_state.hh
@@ -127,7 +127,7 @@ struct ThreadState : public Serializable {
     /** Reads the number of instructions functionally executed and
      * committed.
      */
-    Counter readFuncExeInst() { return funcExeInst; }
+    Counter readFuncExeInst() const { return funcExeInst; }
 
     /** Sets the total number of instructions functionally executed
      * and committed.