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authorGabe Black <gabeblack@google.com>2019-08-17 00:30:46 -0700
committerGabe Black <gabeblack@google.com>2019-08-28 07:58:56 +0000
commit642489740985f2804e8229c69edeb46f2432d8f9 (patch)
treeb2b7b17e4f1d48dd6cebdbfb95b7e91d787faee0 /src
parent9ad74b7d0c0f726e933f3589c69fedc945855e3c (diff)
downloadgem5-642489740985f2804e8229c69edeb46f2432d8f9.tar.xz
cpu, mem: Add new getSendFunctional method to the base CPU.
This returns a sendFunctional delegate references which can be used to send functional accesses directly, or more likely when constructing a PortProxy subclass. In those cases only the functional capabilities of those ports are needed so there's no reason to require a full port which supports all three protocols. Also, this removes the last remaining use of get(Data|Inst)Port which relies on those returning a port which supports the gem5 protocols, except the default implementations of this new function. If a CPU doesn't have traditional gem5 style ports, it can override this function to do whatever other behavior is necessary and return its real ports through get(Data|Inst)Port. Change-Id: Ide4da81e3bc679662cd85902ba6bd537cce54a53 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20237 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/cpu/base.hh10
-rw-r--r--src/cpu/thread_state.cc6
-rw-r--r--src/mem/fs_translating_port_proxy.cc2
3 files changed, 14 insertions, 4 deletions
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 1ca1ca10c..00373a655 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -161,6 +161,16 @@ class BaseCPU : public ClockedObject
virtual MasterPort &getDataPort() = 0;
/**
+ * Returns a sendFunctional delegate for use with port proxies.
+ */
+ virtual PortProxy::SendFunctionalFunc
+ getSendFunctional()
+ {
+ MasterPort &port = getDataPort();
+ return [&port](PacketPtr pkt)->void { port.sendFunctional(pkt); };
+ }
+
+ /**
* Purely virtual method that returns a reference to the instruction
* port. All subclasses must implement this method.
*
diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc
index dc4a624a7..cb9a87ca8 100644
--- a/src/cpu/thread_state.cc
+++ b/src/cpu/thread_state.cc
@@ -109,15 +109,15 @@ ThreadState::initMemProxies(ThreadContext *tc)
assert(physProxy == NULL);
// This cannot be done in the constructor as the thread state
// itself is created in the base cpu constructor and the
- // getDataPort is a virtual function
- physProxy = new PortProxy(baseCpu->getDataPort(),
+ // getSendFunctional is a virtual function
+ physProxy = new PortProxy(baseCpu->getSendFunctional(),
baseCpu->cacheLineSize());
assert(virtProxy == NULL);
virtProxy = new FSTranslatingPortProxy(tc);
} else {
assert(virtProxy == NULL);
- virtProxy = new SETranslatingPortProxy(baseCpu->getDataPort(),
+ virtProxy = new SETranslatingPortProxy(baseCpu->getSendFunctional(),
process,
SETranslatingPortProxy::NextPage);
}
diff --git a/src/mem/fs_translating_port_proxy.cc b/src/mem/fs_translating_port_proxy.cc
index d12af13af..2ef48b098 100644
--- a/src/mem/fs_translating_port_proxy.cc
+++ b/src/mem/fs_translating_port_proxy.cc
@@ -55,7 +55,7 @@
#include "sim/system.hh"
FSTranslatingPortProxy::FSTranslatingPortProxy(ThreadContext *tc)
- : PortProxy(tc->getCpuPtr()->getDataPort(),
+ : PortProxy(tc->getCpuPtr()->getSendFunctional(),
tc->getSystemPtr()->cacheLineSize()), _tc(tc)
{
}