diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-02-23 15:10:49 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-02-23 15:10:49 -0600 |
| commit | 7391ea6de63578722d97c9169e60db5b06754137 (patch) | |
| tree | c544188de95cc72b74467bdec048883f300a5b61 /src | |
| parent | ae3d45685512b75f878eb9d7917680fc3971988e (diff) | |
| download | gem5-7391ea6de63578722d97c9169e60db5b06754137.tar.xz | |
ARM: Do something for ISB, DSB, DMB
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/arm/isa/formats/misc.isa | 9 | ||||
| -rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 11 | ||||
| -rw-r--r-- | src/cpu/o3/commit_impl.hh | 3 |
3 files changed, 13 insertions, 10 deletions
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa index 3bcb5c97d..4a9200504 100644 --- a/src/arch/arm/isa/formats/misc.isa +++ b/src/arch/arm/isa/formats/misc.isa @@ -120,14 +120,11 @@ let {{ return new WarnUnimplemented( isRead ? "mrc dccmvau" : "mcr dccmvau", machInst); case MISCREG_CP15ISB: - return new WarnUnimplemented( - isRead ? "mrc cp15isb" : "mcr cp15isb", machInst); + return new Isb(machInst); case MISCREG_CP15DSB: - return new WarnUnimplemented( - isRead ? "mrc cp15dsb" : "mcr cp15dsb", machInst); + return new Dsb(machInst); case MISCREG_CP15DMB: - return new WarnUnimplemented( - isRead ? "mrc cp15dmb" : "mcr cp15dmb", machInst); + return new Dmb(machInst); case MISCREG_ICIALLUIS: return new WarnUnimplemented( isRead ? "mrc icialluis" : "mcr icialluis", machInst); diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index ad5021daf..be51d927d 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -696,19 +696,23 @@ let {{ exec_output += ClrexCompleteAcc.subst(clrexIop) isbCode = ''' + fault = new FlushPipe; ''' isbIop = InstObjParams("isb", "Isb", "PredOp", {"code": isbCode, - "predicate_test": predicateTest}, ['IsSerializing']) + "predicate_test": predicateTest}, + ['IsSerializeAfter']) header_output += BasicDeclare.subst(isbIop) decoder_output += BasicConstructor.subst(isbIop) exec_output += PredOpExecute.subst(isbIop) dsbCode = ''' + fault = new FlushPipe; ''' dsbIop = InstObjParams("dsb", "Dsb", "PredOp", {"code": dsbCode, - "predicate_test": predicateTest},['IsMemBarrier']) + "predicate_test": predicateTest}, + ['IsMemBarrier', 'IsSerializeAfter']) header_output += BasicDeclare.subst(dsbIop) decoder_output += BasicConstructor.subst(dsbIop) exec_output += PredOpExecute.subst(dsbIop) @@ -717,7 +721,8 @@ let {{ ''' dmbIop = InstObjParams("dmb", "Dmb", "PredOp", {"code": dmbCode, - "predicate_test": predicateTest},['IsMemBarrier']) + "predicate_test": predicateTest}, + ['IsMemBarrier']) header_output += BasicDeclare.subst(dmbIop) decoder_output += BasicConstructor.subst(dmbIop) exec_output += PredOpExecute.subst(dmbIop) diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index 01e235722..104e7fb58 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -1177,7 +1177,8 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) } } #endif - + DPRINTF(Commit, "Committing instruction with [sn:%lli]\n", + head_inst->seqNum); if (head_inst->traceData) { head_inst->traceData->setFetchSeq(head_inst->seqNum); head_inst->traceData->setCPSeq(thread[tid]->numInst); |