cpu: Make get(Data|Inst)Port return a Port and not a MasterPort.

No caller uses any of the MasterPort specific properties of these
function's return values, so we can instead return a reference to the
base Port class. This makes it possible for the data and inst ports
to be of any port type, not just gem5 style MasterPorts. This makes
life simpler for, for example, systemc based CPUs which might have TLM
ports.

It also makes it possible for any two CPUs which have compatible ports
to be switched between, as long as the ports they use support being
unbound. Unfortunately that does not include TLM or systemc ports which
are bound permanently.

Change-Id: I98fce5a16d2ef1af051238e929dd96d57a4ac838
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20240
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

9 files changed, 25 insertions, 20 deletions

diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 00373a655..dfee21fab 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -158,7 +158,7 @@ class BaseCPU : public ClockedObject
      *
      * @return a reference to the data port
      */
-    virtual MasterPort &getDataPort() = 0;
+    virtual Port &getDataPort() = 0;
 
     /**
      * Returns a sendFunctional delegate for use with port proxies.
@@ -166,8 +166,9 @@ class BaseCPU : public ClockedObject
     virtual PortProxy::SendFunctionalFunc
     getSendFunctional()
     {
-        MasterPort &port = getDataPort();
-        return [&port](PacketPtr pkt)->void { port.sendFunctional(pkt); };
+        auto port = dynamic_cast<MasterPort *>(&getDataPort());
+        assert(port);
+        return [port](PacketPtr pkt)->void { port->sendFunctional(pkt); };
     }
 
     /**
@@ -176,7 +177,7 @@ class BaseCPU : public ClockedObject
      *
      * @return a reference to the instruction port
      */
-    virtual MasterPort &getInstPort() = 0;
+    virtual Port &getInstPort() = 0;
 
     /** Reads this CPU's ID. */
     int cpuId() const { return _cpuId; }
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 66632b720..440fe81b5 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -105,7 +105,8 @@ class CheckerCPU : public BaseCPU, public ExecContext
 
     void setDcachePort(MasterPort *dcache_port);
 
-    MasterPort &getDataPort() override
+    Port &
+    getDataPort() override
     {
         // the checker does not have ports on its own so return the
         // data port of the actual CPU core
@@ -113,7 +114,8 @@ class CheckerCPU : public BaseCPU, public ExecContext
         return *dcachePort;
     }
 
-    MasterPort &getInstPort() override
+    Port &
+    getInstPort() override
     {
         // the checker does not have ports on its own so return the
         // data port of the actual CPU core
diff --git a/src/cpu/kvm/base.hh b/src/cpu/kvm/base.hh
index a22637f98..7bf518f04 100644
--- a/src/cpu/kvm/base.hh
+++ b/src/cpu/kvm/base.hh
@@ -97,8 +97,8 @@ class BaseKvmCPU : public BaseCPU
 
     void verifyMemoryMode() const override;
 
-    MasterPort &getDataPort() override { return dataPort; }
-    MasterPort &getInstPort() override { return instPort; }
+    Port &getDataPort() override { return dataPort; }
+    Port &getInstPort() override { return instPort; }
 
     void wakeup(ThreadID tid = 0) override;
     void activateContext(ThreadID thread_num) override;
diff --git a/src/cpu/minor/cpu.cc b/src/cpu/minor/cpu.cc
index 63efde2dc..ddba0cdaa 100644
--- a/src/cpu/minor/cpu.cc
+++ b/src/cpu/minor/cpu.cc
@@ -321,12 +321,14 @@ MinorCPUParams::create()
     return new MinorCPU(this);
 }
 
-MasterPort &MinorCPU::getInstPort()
+Port &
+MinorCPU::getInstPort()
 {
     return pipeline->getInstPort();
 }
 
-MasterPort &MinorCPU::getDataPort()
+Port &
+MinorCPU::getDataPort()
 {
     return pipeline->getDataPort();
 }
diff --git a/src/cpu/minor/cpu.hh b/src/cpu/minor/cpu.hh
index 4e4762390..e85b67fbe 100644
--- a/src/cpu/minor/cpu.hh
+++ b/src/cpu/minor/cpu.hh
@@ -114,10 +114,10 @@ class MinorCPU : public BaseCPU
     Enums::ThreadPolicy threadPolicy;
   protected:
      /** Return a reference to the data port. */
-    MasterPort &getDataPort() override;
+    Port &getDataPort() override;
 
     /** Return a reference to the instruction port. */
-    MasterPort &getInstPort() override;
+    Port &getInstPort() override;
 
   public:
     MinorCPU(MinorCPUParams *params);
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 58a22184d..ac917dba9 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -735,14 +735,14 @@ class FullO3CPU : public BaseO3CPU
     }
 
     /** Used by the fetch unit to get a hold of the instruction port. */
-    MasterPort &
+    Port &
     getInstPort() override
     {
         return this->fetch.getInstPort();
     }
 
     /** Get the dcache port (used to find block size for translations). */
-    MasterPort &
+    Port &
     getDataPort() override
     {
         return this->iew.ldstQueue.getDataPort();
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index ba52bc933..69ac09e4c 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -174,10 +174,10 @@ class AtomicSimpleCPU : public BaseSimpleCPU
   protected:
 
     /** Return a reference to the data port. */
-    MasterPort &getDataPort() override { return dcachePort; }
+    Port &getDataPort() override { return dcachePort; }
 
     /** Return a reference to the instruction port. */
-    MasterPort &getInstPort() override { return icachePort; }
+    Port &getInstPort() override { return icachePort; }
 
     /** Perform snoop for other cpu-local thread contexts. */
     void threadSnoop(PacketPtr pkt, ThreadID sender);
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index e423ae8e2..53e0ed7e1 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -264,10 +264,10 @@ class TimingSimpleCPU : public BaseSimpleCPU
   protected:
 
      /** Return a reference to the data port. */
-    MasterPort &getDataPort() override { return dcachePort; }
+    Port &getDataPort() override { return dcachePort; }
 
     /** Return a reference to the instruction port. */
-    MasterPort &getInstPort() override { return icachePort; }
+    Port &getInstPort() override { return icachePort; }
 
   public:
 
diff --git a/src/cpu/trace/trace_cpu.hh b/src/cpu/trace/trace_cpu.hh
index c873a349f..ebc14ca81 100644
--- a/src/cpu/trace/trace_cpu.hh
+++ b/src/cpu/trace/trace_cpu.hh
@@ -1146,10 +1146,10 @@ class TraceCPU : public BaseCPU
   public:
 
     /** Used to get a reference to the icache port. */
-    MasterPort &getInstPort() { return icachePort; }
+    Port &getInstPort() { return icachePort; }
 
     /** Used to get a reference to the dcache port. */
-    MasterPort &getDataPort() { return dcachePort; }
+    Port &getDataPort() { return dcachePort; }
 
     void regStats();
 };