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| author | Daniel R. Carvalho <odanrc@yahoo.com.br> | 2018-11-29 16:33:24 +0100 |
|---|---|---|
| committer | Daniel Carvalho <odanrc@yahoo.com.br> | 2019-03-07 13:07:09 +0000 |
| commit | 7770e6a972d8dd8742724533fe4c4635d8aabf2c (patch) | |
| tree | 71a270f66dda70cc28eb0a20403df1f708724d2c /src | |
| parent | 97281129c9b24ce51d4c9ad2f5bba4b15c375e14 (diff) | |
| download | gem5-7770e6a972d8dd8742724533fe4c4635d8aabf2c.tar.xz | |
mem-cache: Fix recvTimingReq doWritebacks tick
Before being sent to the writebuffer, the evicted blocks
must be selected for replacement, and therefore the
access latency must be applied. The forward latency is
then applied on top of that delay.
Change-Id: I16a25a8bf6051f63eb7a02fe66acb6af26d434fc
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14736
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mem/cache/base.cc | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index d4e93c0ef..204377044 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -355,9 +355,10 @@ BaseCache::recvTimingReq(PacketPtr pkt) // access() will set the lat value. satisfied = access(pkt, blk, lat, writebacks); - // copy writebacks to write buffer here to ensure they logically - // precede anything happening below - doWritebacks(writebacks, forward_time); + // After the evicted blocks are selected, they must be forwarded + // to the write buffer to ensure they logically precede anything + // happening below + doWritebacks(writebacks, clockEdge(lat + forwardLatency)); } // Here we charge the headerDelay that takes into account the latencies |