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| author | Adrià Armejach <adria.armejach@bsc.es> | 2019-12-18 15:40:17 +0100 |
|---|---|---|
| committer | Adria Armejach <adria.armejach@gmail.com> | 2019-12-19 11:46:41 +0000 |
| commit | 77b6f50ce382b37801c63f8a0d06c02bedbfcafa (patch) | |
| tree | faa6eed9f0e4df8dd400b623ce7d7dfefda1effc /src | |
| parent | c4724cac6b75ae9a9f32715f1acfa2d20dcd6fcc (diff) | |
| download | gem5-77b6f50ce382b37801c63f8a0d06c02bedbfcafa.tar.xz | |
arch-arm: Fix decoding of LDFF1x scalar plus scalar
First-faulting loads do allow Rm == 0x1f.
Change-Id: Ib9bcb55e126653813fdbb7c29970af23a2471ebb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23803
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/arm/isa/formats/sve_2nd_level.isa | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/arch/arm/isa/formats/sve_2nd_level.isa b/src/arch/arm/isa/formats/sve_2nd_level.isa index c06d7f6a7..8bde189b2 100644 --- a/src/arch/arm/isa/formats/sve_2nd_level.isa +++ b/src/arch/arm/isa/formats/sve_2nd_level.isa @@ -3132,10 +3132,6 @@ namespace Aarch64 IntRegIndex rm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16); IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10); - if (rm == 0x1f) { - return new Unknown64(machInst); - } - return decodeSveContigLoadSSInsts<SveContigFFLoadSS>( bits(machInst, 24, 21), machInst, zt, pg, rn, rm, true); } // decodeSveContigFFLoadSS |