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| author | Gabor Dozsa <gabor.dozsa@arm.com> | 2019-01-23 15:15:16 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2020-01-07 17:47:43 +0000 |
| commit | 80c51fc6015420eace7eea3c82d9ddc7900da08c (patch) | |
| tree | a7e64e14316f5dc24b3e532b7db90cf7e3a04fd2 /src | |
| parent | 6816e3e39fd5a23098d9997062e7c35952ad95dd (diff) | |
| download | gem5-80c51fc6015420eace7eea3c82d9ddc7900da08c.tar.xz | |
cpu: Disable O3CPU value forwarding with write strobes
https://gem5-review.googlesource.com/c/public/gem5/+/19173 did the same
for MinorCPU
Change-Id: I22d631a3d2032570f6e84b0f5eb018d1f84414ef
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23952
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/o3/lsq_unit.hh | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index 7c3e0e026..e15d01b26 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -725,7 +725,10 @@ LSQUnit<Impl>::read(LSQRequest *req, int load_idx) store_has_lower_limit && store_has_upper_limit && !req->mainRequest()->isLLSC()) { - coverage = AddrRangeCoverage::FullAddrRangeCoverage; + const auto& store_req = store_it->request()->mainRequest(); + coverage = store_req->isMasked() ? + AddrRangeCoverage::PartialAddrRangeCoverage : + AddrRangeCoverage::FullAddrRangeCoverage; } else if ( // This is the partial store-load forwarding case where a store // has only part of the load's data and the load isn't LLSC |