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| author | Gabe Black <gabeblack@google.com> | 2020-01-09 01:08:09 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2020-01-14 02:19:19 +0000 |
| commit | 80c5add40b096e29fa45d266104af54733f925f0 (patch) | |
| tree | b87ae87e9f8980c1b8caa51be91b4422592253da /src | |
| parent | 8a3ba27dfe5e5b716b9b35e0ef62c40d5b5cc223 (diff) | |
| download | gem5-80c5add40b096e29fa45d266104af54733f925f0.tar.xz | |
x86: Stop clearing RAX for BIST in initCPU.
This doesn't actually change any behavior since RAX was being zeroed
anyway, but since we don't and almost certainly never will have a BIST
and the BIST is optional even in real hardware, we can drop it and
simplify initCPU a little further.
This reduces x86's initCPU function to just an invocation of
InitInterrupt's invoke.
Change-Id: I56b1aae2c1a738ef7ffabcf648dd7d0fb819d4e0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24187
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/x86/utility.cc | 11 |
1 files changed, 1 insertions, 10 deletions
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc index b00e6867f..75f242d83 100644 --- a/src/arch/x86/utility.cc +++ b/src/arch/x86/utility.cc @@ -74,16 +74,7 @@ getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) void initCPU(ThreadContext *tc, int cpuId) { - // This function is essentially performing a reset. The actual INIT - // interrupt does a subset of this, so we'll piggyback on some of its - // functionality. - InitInterrupt init(0); - init.invoke(tc); - - // Set integer register EAX to 0 to indicate that the optional BIST - // passed. No BIST actually runs, but software may still check this - // register for errors. - tc->setIntReg(INTREG_RAX, 0); + InitInterrupt(0).invoke(tc); } void startupCPU(ThreadContext *tc, int cpuId) |