diff options
author | Gabe Black <gabeblack@google.com> | 2019-04-28 08:56:22 +0000 |
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committer | Gabe Black <gabeblack@google.com> | 2019-04-29 22:57:37 +0000 |
commit | 88fc141f72bea768fdf8d6e22611a89f135cfc10 (patch) | |
tree | 4e2292f8964180263805ea379a86d8ec72faa678 /src | |
parent | a632ee72adc7056786752973ecfa44ae01fca137 (diff) | |
download | gem5-88fc141f72bea768fdf8d6e22611a89f135cfc10.tar.xz |
cpu: Get rid of the (read|set)RegOtherThread methods.
These are implemented by MIPS internally now.
Change-Id: If7465e1666e51e1314968efb56a5a814e62ee2d1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18436
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src')
-rw-r--r-- | src/cpu/checker/cpu.hh | 15 | ||||
-rw-r--r-- | src/cpu/exec_context.hh | 14 | ||||
-rw-r--r-- | src/cpu/minor/exec_context.hh | 45 | ||||
-rw-r--r-- | src/cpu/o3/dyn_inst.hh | 15 | ||||
-rw-r--r-- | src/cpu/simple/exec_context.hh | 19 | ||||
-rw-r--r-- | src/cpu/thread_context.hh | 11 |
6 files changed, 0 insertions, 119 deletions
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 5f830d7a9..96f6cc7d4 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -483,21 +483,6 @@ class CheckerCPU : public BaseCPU, public ExecContext return this->setMiscReg(reg.index(), val); } -#if THE_ISA == MIPS_ISA - RegVal - readRegOtherThread(const RegId &misc_reg, ThreadID tid) override - { - panic("MIPS MT not defined for CheckerCPU.\n"); - return 0; - } - - void - setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid) override - { - panic("MIPS MT not defined for CheckerCPU.\n"); - } -#endif - ///////////////////////////////////////// void diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh index d46cc1315..58d756c6d 100644 --- a/src/cpu/exec_context.hh +++ b/src/cpu/exec_context.hh @@ -353,20 +353,6 @@ class ExecContext { virtual AddressMonitor *getAddrMonitor() = 0; /** @} */ - - /** - * @{ - * @name MIPS-Specific Interfaces - */ - -#if THE_ISA == MIPS_ISA - virtual RegVal readRegOtherThread(const RegId ®, - ThreadID tid=InvalidThreadID) = 0; - virtual void setRegOtherThread(const RegId& reg, RegVal val, - ThreadID tid=InvalidThreadID) = 0; -#endif - - /** @} */ }; #endif // __CPU_EXEC_CONTEXT_HH__ diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh index 02b3dae1c..4ac621aea 100644 --- a/src/cpu/minor/exec_context.hh +++ b/src/cpu/minor/exec_context.hh @@ -441,51 +441,6 @@ class ExecContext : public ::ExecContext BaseCPU *getCpuPtr() { return &cpu; } - /* MIPS: other thread register reading/writing */ - RegVal - readRegOtherThread(const RegId ®, ThreadID tid=InvalidThreadID) - { - SimpleThread *other_thread = (tid == InvalidThreadID - ? &thread : cpu.threads[tid]); - - switch (reg.classValue()) { - case IntRegClass: - return other_thread->readIntReg(reg.index()); - break; - case FloatRegClass: - return other_thread->readFloatReg(reg.index()); - break; - case MiscRegClass: - return other_thread->readMiscReg(reg.index()); - default: - panic("Unexpected reg class! (%s)", - reg.className()); - return 0; - } - } - - void - setRegOtherThread(const RegId ®, RegVal val, - ThreadID tid=InvalidThreadID) - { - SimpleThread *other_thread = (tid == InvalidThreadID - ? &thread : cpu.threads[tid]); - - switch (reg.classValue()) { - case IntRegClass: - return other_thread->setIntReg(reg.index(), val); - break; - case FloatRegClass: - return other_thread->setFloatReg(reg.index(), val); - break; - case MiscRegClass: - return other_thread->setMiscReg(reg.index(), val); - default: - panic("Unexpected reg class! (%s)", - reg.className()); - } - } - public: // monitor/mwait funtions void armMonitor(Addr address) override diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh index 24c59a25d..01886606e 100644 --- a/src/cpu/o3/dyn_inst.hh +++ b/src/cpu/o3/dyn_inst.hh @@ -429,21 +429,6 @@ class BaseO3DynInst : public BaseDynInst<Impl> this->cpu->setCCReg(this->_destRegIdx[idx], val); BaseDynInst<Impl>::setCCRegOperand(si, idx, val); } - -#if THE_ISA == MIPS_ISA - RegVal - readRegOtherThread(const RegId& misc_reg, ThreadID tid) override - { - panic("MIPS MT not defined for O3 CPU.\n"); - return 0; - } - - void - setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid) override - { - panic("MIPS MT not defined for O3 CPU.\n"); - } -#endif }; #endif // __CPU_O3_ALPHA_DYN_INST_HH__ diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh index de5cc7fd7..b49747dd2 100644 --- a/src/cpu/simple/exec_context.hh +++ b/src/cpu/simple/exec_context.hh @@ -566,25 +566,6 @@ class SimpleExecContext : public ExecContext { { return cpu->getCpuAddrMonitor(thread->threadId()); } - -#if THE_ISA == MIPS_ISA - RegVal - readRegOtherThread(const RegId& reg, ThreadID tid=InvalidThreadID) - override - { - panic("Simple CPU models do not support multithreaded " - "register access."); - } - - void - setRegOtherThread(const RegId& reg, RegVal val, - ThreadID tid=InvalidThreadID) override - { - panic("Simple CPU models do not support multithreaded " - "register access."); - } -#endif - }; #endif // __CPU_EXEC_CONTEXT_HH__ diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index 09f2a1eab..00e97b23c 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -299,17 +299,6 @@ class ThreadContext virtual RegId flattenRegId(const RegId& regId) const = 0; - virtual RegVal - readRegOtherThread(const RegId& misc_reg, ThreadID tid) - { - return 0; - } - - virtual void - setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid) - { - } - // Also not necessarily the best location for these two. Hopefully will go // away once we decide upon where st cond failures goes. virtual unsigned readStCondFailures() const = 0; |