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authorAndreas Hansson <andreas.hansson@arm.com>2012-10-15 08:07:07 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-10-15 08:07:07 -0400
commit930db9257dbac7e678888a65a17c39bcc87aa7fa (patch)
tree0963906363267079f8cab73332e926320cbd242e /src
parent8cc503f1dd535690a9e50188d0216844057125f8 (diff)
downloadgem5-930db9257dbac7e678888a65a17c39bcc87aa7fa.tar.xz
Clock: Inherit the clock from parent by default
This patch changes the default 1 Tick clock period to a proxy that resolves the parents clock. As a result of this, the caches and L1-to-L2 bus, for example, will automatically use the clock period of the CPU unless explicitly overridden. To ensure backwards compatibility, the System class overrides the proxy and specifies a 1 Tick clock. We could change this to something more reasonable in a follow-on patch, perhaps 1 GHz or something similar. With this patch applied, all clocked objects should have a reasonable clock period set, and could start specifying delays in Cycles instead of absolute time.
Diffstat (limited to 'src')
-rw-r--r--src/sim/ClockedObject.py6
-rw-r--r--src/sim/System.py7
2 files changed, 12 insertions, 1 deletions
diff --git a/src/sim/ClockedObject.py b/src/sim/ClockedObject.py
index 9bb243df8..26b0e2348 100644
--- a/src/sim/ClockedObject.py
+++ b/src/sim/ClockedObject.py
@@ -37,9 +37,13 @@
from m5.SimObject import SimObject
from m5.params import *
+from m5.proxy import *
class ClockedObject(SimObject):
type = 'ClockedObject'
abstract = True
- clock = Param.Clock('1t', "Clock speed")
+ # Clock period of this object, with the default value being the
+ # clock period of the parent object, unproxied at instantiation
+ # time
+ clock = Param.Clock(Parent.clock, "Clock speed")
diff --git a/src/sim/System.py b/src/sim/System.py
index f680e64bf..88afea873 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -41,6 +41,13 @@ class System(MemObject):
type = 'System'
system_port = MasterPort("System port")
+ # Override the clock from the ClockedObject which looks at the
+ # parent clock by default
+ clock = '1t'
+ # @todo Either make this value 0 and treat it as an error if it is
+ # not overridden, or choose a more sensible value in the range of
+ # 1GHz
+
@classmethod
def export_method_cxx_predecls(cls, code):
code('#include "sim/system.hh"')