diff options
| author | Gabe Black <gabeblack@google.com> | 2019-10-20 01:06:49 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-10-21 17:07:29 +0000 |
| commit | 9a8d60da0e6bc416fc53606aae60167506e75c4e (patch) | |
| tree | 2a71c46882c47a341dd045000a612f65f8797bb3 /src | |
| parent | b14ad982672c9ac07a3da55594dd15fb09eb51a5 (diff) | |
| download | gem5-9a8d60da0e6bc416fc53606aae60167506e75c4e.tar.xz | |
cpu: Apply the ARM TLB rework to the checker CPU.
The TLBs now create the stage 2 MMUs as children, and since those are
specialized for instruction and data, the CPU needs to use ArmITB or
ArmDTB instead of ArmTLB which is the base class without an MMU. This
was changed for the BaseCPU already, but the TLBs are added in the
checker CPU as well.
Change-Id: Ide8ce950622b40f69c37bbe2ea0d22295b76d7a6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21979
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/simple/BaseSimpleCPU.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/simple/BaseSimpleCPU.py b/src/cpu/simple/BaseSimpleCPU.py index 6714295d2..f8e2948c9 100644 --- a/src/cpu/simple/BaseSimpleCPU.py +++ b/src/cpu/simple/BaseSimpleCPU.py @@ -42,11 +42,11 @@ class BaseSimpleCPU(BaseCPU): def addCheckerCpu(self): if buildEnv['TARGET_ISA'] in ['arm']: - from m5.objects.ArmTLB import ArmTLB + from m5.objects.ArmTLB import ArmITB, ArmDTB self.checker = DummyChecker(workload = self.workload) - self.checker.itb = ArmTLB(size = self.itb.size) - self.checker.dtb = ArmTLB(size = self.dtb.size) + self.checker.itb = ArmITB(size = self.itb.size) + self.checker.dtb = ArmDTB(size = self.dtb.size) else: print("ERROR: Checker only supported under ARM ISA!") exit(1) |