diff options
| author | Gabe Black <gabeblack@google.com> | 2019-10-15 21:48:31 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-10-19 01:49:55 +0000 |
| commit | 9d3b9e96c56386ee6539657c21cba95e118e576a (patch) | |
| tree | 2a6fc39778e534c827f048320fcb89a75e8f9dfb /src | |
| parent | b6ef760ebb39e813526ba7abc3e05d7f449c9e32 (diff) | |
| download | gem5-9d3b9e96c56386ee6539657c21cba95e118e576a.tar.xz | |
cpu,arm: Push the stage 2 MMUs out of the CPU into the TLBs.
This regularizes the TLB setup in the CPU so that ARM is no longer a
special case with extra objects.
Change-Id: I739b82578ff74f8f9777cd7e34cd5227b47b186c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21842
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/arm/ArmTLB.py | 10 | ||||
| -rw-r--r-- | src/cpu/BaseCPU.py | 8 |
2 files changed, 10 insertions, 8 deletions
diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py index 4a6b3e7cd..d2334630e 100644 --- a/src/arch/arm/ArmTLB.py +++ b/src/arch/arm/ArmTLB.py @@ -90,11 +90,17 @@ class ArmStage2MMU(SimObject): class ArmStage2IMMU(ArmStage2MMU): # We rely on the itb being a parameter of the CPU, and get the # appropriate object that way - tlb = Parent.itb + tlb = Parent.any stage2_tlb = ArmStage2TLB() class ArmStage2DMMU(ArmStage2MMU): # We rely on the dtb being a parameter of the CPU, and get the # appropriate object that way - tlb = Parent.dtb + tlb = Parent.any stage2_tlb = ArmStage2TLB() + +class ArmITB(ArmTLB): + stage2_mmu = ArmStage2IMMU() + +class ArmDTB(ArmTLB): + stage2_mmu = ArmStage2DMMU() diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index e17e26a11..57f0f2f3d 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -83,8 +83,7 @@ elif buildEnv['TARGET_ISA'] == 'mips': from m5.objects.MipsISA import MipsISA as ArchISA ArchISAsParam = VectorParam.MipsISA elif buildEnv['TARGET_ISA'] == 'arm': - from m5.objects.ArmTLB import ArmTLB as ArchDTB, ArmTLB as ArchITB - from m5.objects.ArmTLB import ArmStage2IMMU, ArmStage2DMMU + from m5.objects.ArmTLB import ArmDTB as ArchDTB, ArmITB as ArchITB from m5.objects.ArmInterrupts import ArmInterrupts as ArchInterrupts from m5.objects.ArmISA import ArmISA as ArchISA ArchISAsParam = VectorParam.ArmISA @@ -174,10 +173,7 @@ class BaseCPU(ClockedObject): dtb = Param.BaseTLB(ArchDTB(), "Data TLB") itb = Param.BaseTLB(ArchITB(), "Instruction TLB") - if buildEnv['TARGET_ISA'] == 'arm': - istage2_mmu = ArmStage2IMMU() - dstage2_mmu = ArmStage2DMMU() - elif buildEnv['TARGET_ISA'] == 'power': + if buildEnv['TARGET_ISA'] == 'power': UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") interrupts = VectorParam.BaseInterrupts([], "Interrupt Controller") isa = ArchISAsParam([], "ISA instance") |