summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:03 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:03 -0500
commita8eb9d521c9f94c19bde099edf678f0fb21f7f85 (patch)
tree2213ca4524467feb1b633f327c2511f5fe8847ec /src
parentb02c7f1bcd4fab4097b9b4b99d08a8287ae25ca8 (diff)
downloadgem5-a8eb9d521c9f94c19bde099edf678f0fb21f7f85.tar.xz
ARM: Eliminate the unused rhi and rlo operands.
Diffstat (limited to 'src')
-rw-r--r--src/arch/arm/intregs.hh2
-rw-r--r--src/arch/arm/isa/operands.isa2
2 files changed, 0 insertions, 4 deletions
diff --git a/src/arch/arm/intregs.hh b/src/arch/arm/intregs.hh
index 15499601a..d13cca6df 100644
--- a/src/arch/arm/intregs.hh
+++ b/src/arch/arm/intregs.hh
@@ -96,8 +96,6 @@ enum IntRegIndex
INTREG_ZERO, // Dummy zero reg since there has to be one.
INTREG_UREG0,
- INTREG_RHI,
- INTREG_RLO,
INTREG_CONDCODES,
NUM_INTREGS,
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 2621106ac..d80c0c712 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -109,8 +109,6 @@ def operands {{
'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite),
'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite),
- 'Rhi': ('IntReg', 'uw', 'INTREG_RHI', 'IsInteger', 7),
- 'Rlo': ('IntReg', 'uw', 'INTREG_RLO', 'IsInteger', 8),
'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9),
'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 10),