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| author | Chuan Zhu <chuan.zhu@arm.com> | 2018-01-15 16:14:11 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-02-08 09:27:25 +0000 |
| commit | b885dc68a26e0c7a401ca4b338d997ac577847a8 (patch) | |
| tree | 6e7ec04faf2f3c928f5ad836ec834293a273df5c /src | |
| parent | b05a197d4c1d1c255eb90a7da302149414ebb0cf (diff) | |
| download | gem5-b885dc68a26e0c7a401ca4b338d997ac577847a8.tar.xz | |
arch-arm: Handle route to EL2 in Supervisor Trap
Supervisor Trap is supposed to be able to handle exceptions routed
to EL2, which is enabled by HCR_EL2.TGE. This fix adds routeToHyp()
function to Supervisor Trap to handle this, similar to that in
UndefinedFault, DataAbort, etc.
Change-Id: I1fcf9f2d445ecbc13c8f6d3b7d599728b0250ab7
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7961
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/arm/faults.cc | 31 | ||||
| -rw-r--r-- | src/arch/arm/faults.hh | 4 |
2 files changed, 32 insertions, 3 deletions
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index d143056b1..27894e0c1 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010, 2012-2014, 2016-2017 ARM Limited + * Copyright (c) 2010, 2012-2014, 2016-2018 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -923,10 +923,37 @@ SecureMonitorCall::ec(ThreadContext *tc) const return (from64 ? EC_SMC_64 : vals.ec); } +bool +SupervisorTrap::routeToHyp(ThreadContext *tc) const +{ + bool toHyp = false; + + SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); + HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); + CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); + + // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector + toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.el == EL0); + return toHyp; +} + +uint32_t +SupervisorTrap::iss() const +{ + // If SupervisorTrap is routed to hypervisor, iss field is 0. + if (hypRouted) { + return 0; + } + return issRaw; +} + ExceptionClass SupervisorTrap::ec(ThreadContext *tc) const { - return (overrideEc != EC_INVALID) ? overrideEc : vals.ec; + if (hypRouted) + return EC_UNKNOWN; + else + return (overrideEc != EC_INVALID) ? overrideEc : vals.ec; } ExceptionClass diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh index fa6740a1a..bec2c0e8f 100644 --- a/src/arch/arm/faults.hh +++ b/src/arch/arm/faults.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010, 2012-2013, 2016-2017 ARM Limited + * Copyright (c) 2010, 2012-2013, 2016-2018 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -335,6 +335,8 @@ class SupervisorTrap : public ArmFaultVals<SupervisorTrap> overrideEc(_overrideEc) {} + bool routeToHyp(ThreadContext *tc) const override; + uint32_t iss() const override; ExceptionClass ec(ThreadContext *tc) const override; }; |