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| author | Nikos Nikoleris <nikos.nikoleris@gmail.com> | 2014-02-02 16:37:35 +0100 |
|---|---|---|
| committer | Nikos Nikoleris <nikos.nikoleris@gmail.com> | 2014-02-02 16:37:35 +0100 |
| commit | c6279f2d19cf3d8b625ffcd54b1d0183c1986fe1 (patch) | |
| tree | 645533efc82d7e79c3b75f9326a77a8335d28feb /src | |
| parent | 35266761659ce3efbc1a7e7f1289d90aeddb7db8 (diff) | |
| download | gem5-c6279f2d19cf3d8b625ffcd54b1d0183c1986fe1.tar.xz | |
x86, kvm: Fix bug in the RFlags get and set functions
The getRFlags and setRFlags utility functions were not updated
correctly when condition registers were separated into their own
register class. This lead to incorrect state transfer in calls from
kvm into the simulator (e.g., m5 readfile ended up in an infinite
loop) and when switching CPUs. This patch makes these utility
functions use getCCReg and setCCReg instead of getIntReg and setIntReg
which read and write the integer registers.
Reviewed-by: Andreas Sandberg <andreas@sandberg.pp.se>
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/x86/utility.cc | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc index f7358341b..8f1a419f1 100644 --- a/src/arch/x86/utility.cc +++ b/src/arch/x86/utility.cc @@ -261,9 +261,9 @@ uint64_t getRFlags(ThreadContext *tc) { const uint64_t ncc_flags(tc->readMiscRegNoEffect(MISCREG_RFLAGS)); - const uint64_t cc_flags(tc->readIntReg(X86ISA::CCREG_ZAPS)); - const uint64_t cfof_bits(tc->readIntReg(X86ISA::CCREG_CFOF)); - const uint64_t df_bit(tc->readIntReg(X86ISA::CCREG_DF)); + const uint64_t cc_flags(tc->readCCReg(X86ISA::CCREG_ZAPS)); + const uint64_t cfof_bits(tc->readCCReg(X86ISA::CCREG_CFOF)); + const uint64_t df_bit(tc->readCCReg(X86ISA::CCREG_DF)); // ecf (PSEUDO(3)) & ezf (PSEUDO(4)) are only visible to // microcode, so we can safely ignore them. @@ -276,13 +276,13 @@ getRFlags(ThreadContext *tc) void setRFlags(ThreadContext *tc, uint64_t val) { - tc->setIntReg(X86ISA::CCREG_ZAPS, val & ccFlagMask); - tc->setIntReg(X86ISA::CCREG_CFOF, val & cfofMask); - tc->setIntReg(X86ISA::CCREG_DF, val & DFBit); + tc->setCCReg(X86ISA::CCREG_ZAPS, val & ccFlagMask); + tc->setCCReg(X86ISA::CCREG_CFOF, val & cfofMask); + tc->setCCReg(X86ISA::CCREG_DF, val & DFBit); // Internal microcode registers (ECF & EZF) - tc->setIntReg(X86ISA::CCREG_ECF, 0); - tc->setIntReg(X86ISA::CCREG_EZF, 0); + tc->setCCReg(X86ISA::CCREG_ECF, 0); + tc->setCCReg(X86ISA::CCREG_EZF, 0); // Update the RFLAGS misc reg with whatever didn't go into the // magic registers. |