alpha: Stop using architecture specific register types.

Change-Id: I4052000014c9f6f9ecefd3f37e58595c61599484
Reviewed-on: https://gem5-review.googlesource.com/c/14461
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

7 files changed, 15 insertions, 23 deletions

diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index cc0c583f0..197bb16ea 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -107,7 +107,7 @@ initIPRs(ThreadContext *tc, int cpuId)
     tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
 }
 
-MiscReg
+RegVal
 ISA::readIpr(int idx, ThreadContext *tc)
 {
     uint64_t retval = 0;        // return value, default 0
diff --git a/src/arch/alpha/idle_event.cc b/src/arch/alpha/idle_event.cc
index 85e1d4410..080dcb22c 100644
--- a/src/arch/alpha/idle_event.cc
+++ b/src/arch/alpha/idle_event.cc
@@ -40,7 +40,7 @@ void
 IdleStartEvent::process(ThreadContext *tc)
 {
     if (tc->getKernelStats()) {
-        MiscReg val = tc->readMiscRegNoEffect(IPR_PALtemp23);
+        RegVal val = tc->readMiscRegNoEffect(IPR_PALtemp23);
         tc->getKernelStats()->setIdleProcess(val, tc);
     }
     remove();
diff --git a/src/arch/alpha/isa.cc b/src/arch/alpha/isa.cc
index 685ddd479..71cf2980a 100644
--- a/src/arch/alpha/isa.cc
+++ b/src/arch/alpha/isa.cc
@@ -74,7 +74,7 @@ ISA::unserialize(CheckpointIn &cp)
 }
 
 
-MiscReg
+RegVal
 ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
 {
     switch (misc_reg) {
@@ -94,7 +94,7 @@ ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
     }
 }
 
-MiscReg
+RegVal
 ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
 {
     switch (misc_reg) {
@@ -114,7 +114,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
 }
 
 void
-ISA::setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid)
+ISA::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
 {
     switch (misc_reg) {
       case MISCREG_FPCR:
@@ -140,7 +140,7 @@ ISA::setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid)
 }
 
 void
-ISA::setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc, ThreadID tid)
+ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc, ThreadID tid)
 {
     switch (misc_reg) {
       case MISCREG_FPCR:
diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh
index 2b183f0e3..f26031d8a 100644
--- a/src/arch/alpha/isa.hh
+++ b/src/arch/alpha/isa.hh
@@ -74,11 +74,11 @@ namespace AlphaISA
 
       public:
 
-        MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
-        MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
+        RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
+        RegVal readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
 
-        void setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid=0);
-        void setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc,
+        void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid=0);
+        void setMiscReg(int misc_reg, RegVal val, ThreadContext *tc,
                         ThreadID tid=0);
 
         void
diff --git a/src/arch/alpha/process.cc b/src/arch/alpha/process.cc
index e8dad9917..00468bbc3 100644
--- a/src/arch/alpha/process.cc
+++ b/src/arch/alpha/process.cc
@@ -222,7 +222,7 @@ AlphaProcess::initState()
     tc->setMiscRegNoEffect(IPR_MCSR, 0);
 }
 
-AlphaISA::IntReg
+RegVal
 AlphaProcess::getSyscallArg(ThreadContext *tc, int &i)
 {
     assert(i < 6);
@@ -230,7 +230,7 @@ AlphaProcess::getSyscallArg(ThreadContext *tc, int &i)
 }
 
 void
-AlphaProcess::setSyscallArg(ThreadContext *tc, int i, AlphaISA::IntReg val)
+AlphaProcess::setSyscallArg(ThreadContext *tc, int i, RegVal val)
 {
     assert(i < 6);
     tc->setIntReg(FirstArgumentReg + i, val);
@@ -248,7 +248,7 @@ AlphaProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
         tc->setIntReg(ReturnValueReg, sysret.returnValue());
     } else {
         // got an error, return details
-        tc->setIntReg(SyscallSuccessReg, (IntReg)-1);
+        tc->setIntReg(SyscallSuccessReg, (RegVal)-1);
         tc->setIntReg(ReturnValueReg, sysret.errnoValue());
     }
 }
diff --git a/src/arch/alpha/process.hh b/src/arch/alpha/process.hh
index 28ecd6819..5f224880a 100644
--- a/src/arch/alpha/process.hh
+++ b/src/arch/alpha/process.hh
@@ -49,10 +49,10 @@ class AlphaProcess : public Process
     void argsInit(int intSize, int pageSize);
 
   public:
-    AlphaISA::IntReg getSyscallArg(ThreadContext *tc, int &i) override;
+    RegVal getSyscallArg(ThreadContext *tc, int &i) override;
     /// Explicitly import the otherwise hidden getSyscallArg
     using Process::getSyscallArg;
-    void setSyscallArg(ThreadContext *tc, int i, AlphaISA::IntReg val) override;
+    void setSyscallArg(ThreadContext *tc, int i, RegVal val) override;
     void setSyscallReturn(ThreadContext *tc,
                           SyscallReturn return_value) override;
 
diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh
index 07c0beeb3..e2e8fedcc 100644
--- a/src/arch/alpha/registers.hh
+++ b/src/arch/alpha/registers.hh
@@ -46,14 +46,6 @@ using AlphaISAInst::MaxInstDestRegs;
 // Locked read/write flags are can't be detected by the ISA parser
 const int MaxMiscDestRegs = AlphaISAInst::MaxMiscDestRegs + 1;
 
-typedef RegVal IntReg;
-
-// floating point register file entry type
-typedef RegVal FloatReg;
-
-// control register file contents
-typedef RegVal MiscReg;
-
 // dummy typedef since we don't have CC regs
 typedef uint8_t CCReg;