x86: Templatize the IntMasterPort.

This makes the IntMasterPort usable with any class, making it possible
to avoid inheriting from IntDevice.

It also makes IntMasterPort inherit directly from QueuedMasterPort,
skipping over MessageMasterPort.

Change-Id: I9d218556c838ea567ced5f6fa4d57a3ec9d28d31
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20821
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

6 files changed, 53 insertions, 51 deletions

diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc
index b7d023537..402b91200 100644
--- a/src/arch/x86/interrupts.cc
+++ b/src/arch/x86/interrupts.cc
@@ -331,7 +331,7 @@ X86ISA::Interrupts::recvMessage(PacketPtr pkt)
 }
 
 
-Tick
+bool
 X86ISA::Interrupts::recvResponse(PacketPtr pkt)
 {
     assert(!pkt->isError());
@@ -343,7 +343,7 @@ X86ISA::Interrupts::recvResponse(PacketPtr pkt)
         regs[APIC_INTERRUPT_COMMAND_LOW] = low;
     }
     DPRINTF(LocalApic, "ICR is now idle.\n");
-    return 0;
+    return true;
 }
 
 
diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh
index 48e350cfc..e48fd4bb3 100644
--- a/src/arch/x86/interrupts.hh
+++ b/src/arch/x86/interrupts.hh
@@ -205,7 +205,7 @@ class Interrupts : public PioDevice, IntDevice
     Tick read(PacketPtr pkt) override;
     Tick write(PacketPtr pkt) override;
     Tick recvMessage(PacketPtr pkt);
-    Tick recvResponse(PacketPtr pkt) override;
+    bool recvResponse(PacketPtr pkt) override;
 
     bool
     triggerTimerInterrupt()
diff --git a/src/dev/x86/i82094aa.cc b/src/dev/x86/i82094aa.cc
index e73eec791..dfadbd945 100644
--- a/src/dev/x86/i82094aa.cc
+++ b/src/dev/x86/i82094aa.cc
@@ -85,12 +85,12 @@ X86ISA::I82094AA::getPort(const std::string &if_name, PortID idx)
         return BasicPioDevice::getPort(if_name, idx);
 }
 
-Tick
+bool
 X86ISA::I82094AA::recvResponse(PacketPtr pkt)
 {
     // Packet instantiated calling sendMessage() in signalInterrupt()
     delete pkt;
-    return 0;
+    return true;
 }
 
 Tick
diff --git a/src/dev/x86/i82094aa.hh b/src/dev/x86/i82094aa.hh
index 17a0da486..d9baf111a 100644
--- a/src/dev/x86/i82094aa.hh
+++ b/src/dev/x86/i82094aa.hh
@@ -106,7 +106,7 @@ class I82094AA : public BasicPioDevice, public IntDevice
     Port &getPort(const std::string &if_name,
                   PortID idx=InvalidPortID) override;
 
-    Tick recvResponse(PacketPtr pkt) override;
+    bool recvResponse(PacketPtr pkt) override;
 
     void signalInterrupt(int line);
     void raiseInterruptPin(int number);
diff --git a/src/dev/x86/intdev.cc b/src/dev/x86/intdev.cc
index e6c068a27..fbc2d518c 100644
--- a/src/dev/x86/intdev.cc
+++ b/src/dev/x86/intdev.cc
@@ -43,27 +43,6 @@
 #include "dev/x86/intdev.hh"
 
 void
-X86ISA::IntDevice::IntMasterPort::sendMessage(ApicList apics,
-                                           TriggerIntMessage message,
-                                           bool timing)
-{
-    ApicList::iterator apicIt;
-    for (apicIt = apics.begin(); apicIt != apics.end(); apicIt++) {
-        PacketPtr pkt = buildIntRequest(*apicIt, message);
-        if (timing) {
-            schedTimingReq(pkt, curTick() + latency);
-            // The target handles cleaning up the packet in timing mode.
-        } else {
-            // ignore the latency involved in the atomic transaction
-            sendAtomic(pkt);
-            assert(pkt->isResponse());
-            // also ignore the latency in handling the response
-            recvResponse(pkt);
-        }
-    }
-}
-
-void
 X86ISA::IntDevice::init()
 {
     if (!intMasterPort.isConnected()) {
diff --git a/src/dev/x86/intdev.hh b/src/dev/x86/intdev.hh
index 1a198db62..f71c9ff9d 100644
--- a/src/dev/x86/intdev.hh
+++ b/src/dev/x86/intdev.hh
@@ -49,10 +49,11 @@
 
 #include "arch/x86/intmessage.hh"
 #include "arch/x86/x86_traits.hh"
-#include "mem/mport.hh"
+#include "mem/tport.hh"
 #include "sim/sim_object.hh"
 
-namespace X86ISA {
+namespace X86ISA
+{
 
 template <class Device>
 class IntSlavePort : public SimpleTimingPort
@@ -85,33 +86,56 @@ class IntSlavePort : public SimpleTimingPort
 
 typedef std::list<int> ApicList;
 
-class IntDevice
+template <class Device>
+class IntMasterPort : public QueuedMasterPort
 {
-  protected:
+    ReqPacketQueue reqQueue;
+    SnoopRespPacketQueue snoopRespQueue;
+
+    Device* device;
+    Tick latency;
 
-    class IntMasterPort : public MessageMasterPort
+  public:
+    IntMasterPort(const std::string& _name, SimObject* _parent,
+                  Device* dev, Tick _latency) :
+        QueuedMasterPort(_name, _parent, reqQueue, snoopRespQueue),
+        reqQueue(*_parent, *this), snoopRespQueue(*_parent, *this),
+        device(dev), latency(_latency)
     {
-        IntDevice* device;
-        Tick latency;
-      public:
-        IntMasterPort(const std::string& _name, SimObject* _parent,
-                      IntDevice* dev, Tick _latency) :
-            MessageMasterPort(_name, _parent), device(dev), latency(_latency)
-        {
-        }
+    }
 
-        Tick recvResponse(PacketPtr pkt)
-        {
-            return device->recvResponse(pkt);
+    bool
+    recvTimingResp(PacketPtr pkt) override
+    {
+        return device->recvResponse(pkt);
+    }
+
+    // This is x86 focused, so if this class becomes generic, this would
+    // need to be moved into a subclass.
+    void
+    sendMessage(X86ISA::ApicList apics, TriggerIntMessage message, bool timing)
+    {
+        for (auto id: apics) {
+            PacketPtr pkt = buildIntRequest(id, message);
+            if (timing) {
+                schedTimingReq(pkt, curTick() + latency);
+                // The target handles cleaning up the packet in timing mode.
+            } else {
+                // ignore the latency involved in the atomic transaction
+                sendAtomic(pkt);
+                assert(pkt->isResponse());
+                // also ignore the latency in handling the response
+                device->recvResponse(pkt);
+            }
         }
+    }
+};
 
-        // This is x86 focused, so if this class becomes generic, this would
-        // need to be moved into a subclass.
-        void sendMessage(ApicList apics,
-                TriggerIntMessage message, bool timing);
-    };
+class IntDevice
+{
+  protected:
 
-    IntMasterPort intMasterPort;
+    IntMasterPort<IntDevice> intMasterPort;
 
   public:
     IntDevice(SimObject * parent, Tick latency = 0) :
@@ -124,11 +148,10 @@ class IntDevice
 
     virtual void init();
 
-    virtual Tick
+    virtual bool
     recvResponse(PacketPtr pkt)
     {
         panic("recvResponse not implemented.\n");
-        return 0;
     }
 };