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authorKevin Lim <ktlim@umich.edu>2006-07-05 16:54:24 -0400
committerKevin Lim <ktlim@umich.edu>2006-07-05 16:54:24 -0400
commitea9697250cf55add36af1548b524ab22d6a2cf94 (patch)
tree23111c4c50543d7264db6d39219175d9abc27c68 /src
parentb973fae85d47a8184204d5d38b32ad3d427ce41c (diff)
downloadgem5-ea9697250cf55add36af1548b524ab22d6a2cf94.tar.xz
Fix up some merge problems.
src/base/traceflags.py: Remove BaseCPU traceflag. src/cpu/o3/alpha/params.hh: Move non-Alpha specific parameters out of this params class. src/cpu/o3/params.hh: Move non-Alpha specific params into this params class. --HG-- extra : convert_revision : e5b652adb47a240376733400e6054c66c50bd514
Diffstat (limited to 'src')
-rw-r--r--src/base/traceflags.py1
-rw-r--r--src/cpu/o3/alpha/params.hh14
-rwxr-xr-xsrc/cpu/o3/params.hh15
3 files changed, 16 insertions, 14 deletions
diff --git a/src/base/traceflags.py b/src/base/traceflags.py
index 9ceba3017..27c24107c 100644
--- a/src/base/traceflags.py
+++ b/src/base/traceflags.py
@@ -51,7 +51,6 @@ baseFlags = [
'Activity',
'AlphaConsole',
'BADADDR',
- 'BaseCPU',
'BE',
'BPredRAS',
'Bus',
diff --git a/src/cpu/o3/alpha/params.hh b/src/cpu/o3/alpha/params.hh
index 8f7364dd0..c618cee08 100644
--- a/src/cpu/o3/alpha/params.hh
+++ b/src/cpu/o3/alpha/params.hh
@@ -54,19 +54,7 @@ class AlphaSimpleParams : public O3Params
#if FULL_SYSTEM
AlphaITB *itb;
AlphaDTB *dtb;
-#else
- std::vector<Process *> workload;
- Process *process;
-#endif // FULL_SYSTEM
-
- MemObject *mem;
-
- BaseCPU *checker;
-
- unsigned decodeToFetchDelay;
- unsigned dispatchWidth;
- unsigned wbWidth;
- unsigned wbDepth;
+#endif
};
#endif // __CPU_O3_ALPHA_PARAMS_HH__
diff --git a/src/cpu/o3/params.hh b/src/cpu/o3/params.hh
index 69a1bb937..ed53fa97a 100755
--- a/src/cpu/o3/params.hh
+++ b/src/cpu/o3/params.hh
@@ -47,6 +47,18 @@ class O3Params : public BaseO3CPU::Params
unsigned activity;
//
+ // Pointers to key objects
+ //
+#if !FULL_SYSTEM
+ std::vector<Process *> workload;
+ Process *process;
+#endif // FULL_SYSTEM
+
+ MemObject *mem;
+
+ BaseCPU *checker;
+
+ //
// Caches
//
// MemInterface *icacheInterface;
@@ -86,7 +98,10 @@ class O3Params : public BaseO3CPU::Params
unsigned commitToIEWDelay;
unsigned renameToIEWDelay;
unsigned issueToExecuteDelay;
+ unsigned dispatchWidth;
unsigned issueWidth;
+ unsigned wbWidth;
+ unsigned wbDepth;
FUPool *fuPool;
//